nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 09:12:24 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: fix build errors using arm toolchain

Browse Source 
- fix duplicated typedef
- fix type conversion in atomics
- skip unalignment check for standard build

Jira HYP-12253

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I5e23e7b173bb1c8192e419cf77dd9e0ba59924b1
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2754184
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Richard Zhao
2022-08-01 11:29:04 -07:00
committed by mobile promotions
parent 3d95f2b803
commit b83d4ed668
3 changed files with 4 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h
View File

@@ -28,6 +28,7 @@
#include <nvgpu/pmu/pmuif/acr.h> #include <nvgpu/pmu/pmuif/acr.h>
#include <nvgpu/pmu/pmuif/pmgr.h> #include <nvgpu/pmu/pmuif/pmgr.h>
#include <nvgpu/pmu/pmuif/rpc.h> #include <nvgpu/pmu/pmuif/rpc.h>
#include <nvgpu/pmu/seq.h>
struct gk20a; struct gk20a;
struct pmu_payload; struct pmu_payload;
@@ -36,9 +37,6 @@ struct pmu_msg;
struct pmu_sequence; struct pmu_sequence;
struct falcon_payload_alloc; struct falcon_payload_alloc;
typedef void (*pmu_callback)(struct gk20a *g, struct pmu_msg *msg, void *param,
u32 status);
struct pmu_cmd { struct pmu_cmd {
struct pmu_hdr hdr; struct pmu_hdr hdr;
union { union {

4
drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h
View File

@@ -93,7 +93,7 @@ typedef struct nvgpu_posix_atomic64 {
\ \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \ NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \
NVGPU_MISRA(Rule, 10_3), "TID 374") \ NVGPU_MISRA(Rule, 10_3), "TID 374") \
tmp = (typeof((v)->v))atomic_fetch_add(&((v)->v), (i)); \ tmp = (typeof(tmp))atomic_fetch_add(&((v)->v), (i)); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3)) \ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3)) \
tmp = __builtin_choose_expr( \ tmp = __builtin_choose_expr( \
IS_SIGNED_LONG_TYPE(i), \ IS_SIGNED_LONG_TYPE(i), \
@@ -116,7 +116,7 @@ typedef struct nvgpu_posix_atomic64 {
\ \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \ NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \
NVGPU_MISRA(Rule, 10_3), "TID 374") \ NVGPU_MISRA(Rule, 10_3), "TID 374") \
tmp = (typeof((v)->v))atomic_fetch_sub(&((v)->v), (i)); \ tmp = (typeof(tmp))atomic_fetch_sub(&((v)->v), (i)); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3)) \ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3)) \
tmp = __builtin_choose_expr( \ tmp = __builtin_choose_expr( \
IS_SIGNED_LONG_TYPE(i), \ IS_SIGNED_LONG_TYPE(i), \

2
drivers/gpu/nvgpu/include/nvgpu/static_analysis.h
View File

@@ -816,7 +816,7 @@ static inline s32 nvgpu_safe_cast_s64_to_s32(s64 sl_a)
* not possible, then the CERT-C violations due to unaligned access need to be * not possible, then the CERT-C violations due to unaligned access need to be
* fixed. * fixed.
*/ */
#if !defined(__ARM_FEATURE_UNALIGNED) #if defined(CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY) && !defined(__ARM_FEATURE_UNALIGNED)
#error "__ARM_FEATURE_UNALIGNED not defined. Check static_analysis.h" #error "__ARM_FEATURE_UNALIGNED not defined. Check static_analysis.h"
#endif #endif