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gpu: nvgpu: unit: increase hal.fb test coverage
This patch adds some corner cases tests to increase coverage. JIRA NVGPU-4413 Change-Id: Ifb58c595a0953fdc91580e3d491a1f04143ad9f6 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2293847 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
committed by
Alex Waterman
parent
30755fef04
commit
b85094e045
@@ -175,7 +175,7 @@ int fb_mmu_fault_gv11b_init_test(struct unit_module *m, struct gk20a *g,
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* gv11b_fb_fault_buffer_size_val, gv11b_fb_read_mmu_fault_inst_lo_hi,
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* gv11b_fb_read_mmu_fault_info
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*
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* Test Type: Feature
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* Test Type: Feature, Error injection
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*
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* Input: fb_mmu_fault_gv11b_init_test
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*
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@@ -187,6 +187,8 @@ int fb_mmu_fault_gv11b_init_test(struct unit_module *m, struct gk20a *g,
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* empty.
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* - Call the gv11b_fb_fault_buf_configure_hw HAL and enable fault buffer.
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* - Enable fault buffer again which shouldn't cause any crash.
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* - While trying to disable the fault buffer, trigger a failure of
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* nvgpu_timeout_init.
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* - Disable the fault buffer.
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* - Enable fault buffer, set the busy bit in fb_mmu_fault_status_r register,
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* disable the fault buffer which should cause an internal timeout. Ensure
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@@ -273,7 +275,7 @@ int fb_mmu_fault_gv11b_handle_fault(struct unit_module *m, struct gk20a *g,
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* Targets: gv11b_fb_handle_bar2_fault, gv11b_fb_mmu_fault_info_dump,
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* gv11b_fb_fault_buf_set_state_hw
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*
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* Test Type: Feature
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* Test Type: Feature, Error injection
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*
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* Input: fb_mmu_fault_gv11b_init_test
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*
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@@ -286,6 +288,8 @@ int fb_mmu_fault_gv11b_handle_fault(struct unit_module *m, struct gk20a *g,
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* and a pointer to the channel)
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* - Call the gv11b_fb_mmu_fault_info_dump and ensure it doesn't cause a crash.
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* - Set the fault_status to non-replayable and call gv11b_fb_handle_bar2_fault.
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* - Set the g->ops.bus.bar2_bind HAL to report a failure and call
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* gv11b_fb_handle_bar2_fault again.
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* - Repeat with the fault buffer disabled.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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@@ -169,6 +169,14 @@ int fb_gm20b_mmu_ctrl_test(struct unit_module *m, struct gk20a *g, void *args)
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"vpr_info_fetch did not fail as expected (1)\n");
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}
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nvgpu_posix_enable_fault_injection(timer_fi, true, 1);
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err = g->ops.fb.vpr_info_fetch(g);
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nvgpu_posix_enable_fault_injection(timer_fi, false, 0);
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if (err != -ETIMEDOUT) {
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unit_return_fail(m,
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"vpr_info_fetch did not fail as expected (2)\n");
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}
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/*
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* Trigger timeout in the gm20b_fb_vpr_info_fetch_wait function on
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* fb_mmu_vpr_info_fetch_v(val) == fb_mmu_vpr_info_fetch_false_v()
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@@ -177,7 +185,7 @@ int fb_gm20b_mmu_ctrl_test(struct unit_module *m, struct gk20a *g, void *args)
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err = g->ops.fb.vpr_info_fetch(g);
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if (err != -ETIMEDOUT) {
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unit_return_fail(m,
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"vpr_info_fetch did not fail as expected (2)\n");
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"vpr_info_fetch did not fail as expected (3)\n");
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}
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return UNIT_SUCCESS;
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@@ -59,6 +59,11 @@ static int hal_bar2_bind_nop(struct gk20a *g, struct nvgpu_mem *bar2_inst)
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return 0;
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}
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static int hal_bar2_bind_fail(struct gk20a *g, struct nvgpu_mem *bar2_inst)
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{
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return -1;
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}
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static u32 hal_fifo_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id)
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{
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return INVAL_ID;
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@@ -107,6 +112,8 @@ int fb_mmu_fault_gv11b_buffer_test(struct unit_module *m, struct gk20a *g,
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u32 get_idx;
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u32 val;
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u32 lo, hi;
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struct nvgpu_posix_fault_inj *timers_fi =
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nvgpu_timers_get_fault_injection();
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if (g->ops.fb.is_fault_buf_enabled(g, 0)) {
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unit_return_fail(m, "fault buffer not disabled as expected\n");
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@@ -134,6 +141,11 @@ int fb_mmu_fault_gv11b_buffer_test(struct unit_module *m, struct gk20a *g,
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/* Enabling again shouldn't cause an issue */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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/* Make nvgpu_timeout_init fail during disable operation */
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nvgpu_posix_enable_fault_injection(timers_fi, true, 0);
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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nvgpu_posix_enable_fault_injection(timers_fi, false, 0);
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/* Disable */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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@@ -247,7 +259,6 @@ int fb_mmu_fault_gv11b_handle_fault(struct unit_module *m, struct gk20a *g,
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/* Same case but ensure fault status register is also set properly */
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nvgpu_writel(g, fb_mmu_fault_status_r(),
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fb_mmu_fault_status_non_replayable_overflow_m());
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nvgpu_writel(g, fb_mmu_fault_status_r(), 0);
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (5)\n");
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@@ -257,7 +268,6 @@ int fb_mmu_fault_gv11b_handle_fault(struct unit_module *m, struct gk20a *g,
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nvgpu_writel(g, fb_mmu_fault_status_r(),
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fb_mmu_fault_status_non_replayable_overflow_m() |
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fb_mmu_fault_status_non_replayable_getptr_corrupted_m());
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nvgpu_writel(g, fb_mmu_fault_status_r(), 0);
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (6)\n");
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@@ -298,6 +308,12 @@ int fb_mmu_fault_gv11b_handle_bar2_fault(struct unit_module *m, struct gk20a *g,
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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gv11b_fb_handle_bar2_fault(g, &mmufault, fault_status);
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/* Case where g->ops.bus.bar2_bind fails */
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g->ops.bus.bar2_bind = hal_bar2_bind_fail;
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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gv11b_fb_handle_bar2_fault(g, &mmufault, fault_status);
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g->ops.bus.bar2_bind = hal_bar2_bind_nop;
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/* Case where fault buffer is not enabled */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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gv11b_fb_handle_bar2_fault(g, &mmufault, fault_status);
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