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gpu: nvgpu: gp10b: Fix caching attribute

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Fix caching attribute on 5-level page tables.

Bug 1525976

Change-Id: I5c5bf336d87c642f42a387206a55a889e6e07ba6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737923
This commit is contained in:
Terje Bergstrom
2015-04-30 13:30:28 -07:00
committed by Deepak Nibade
parent b9999f25cc
commit ba61cc7793
1 changed files with 10 additions and 11 deletions
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21
drivers/gpu/nvgpu/gp10b/mm_gp10b.c
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@@ -170,6 +170,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
pde_v[0] |= gmmu_new_pde_aperture_video_memory_f();
pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
pde_v[0] |= gmmu_new_pde_vol_true_f();
pde = pde3_from_index(parent, i);
@@ -259,24 +260,22 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
if (*iova) {
if (unmapped_pte)
pte_w[0] = gmmu_new_pte_valid_false_f() |
gmmu_new_pte_address_sys_f(*iova
>> gmmu_new_pte_address_shift_v());
pte_w[0] = gmmu_new_pte_valid_false_f();
else
pte_w[0] = gmmu_new_pte_valid_true_f() |
gmmu_new_pte_address_sys_f(*iova
>> gmmu_new_pte_address_shift_v());
pte_w[0] = gmmu_new_pte_valid_true_f();
pte_w[0] |= gmmu_new_pte_aperture_video_memory_f() |
gmmu_new_pte_address_sys_f(*iova
>> gmmu_new_pte_address_shift_v());
pte_w[1] = gmmu_new_pte_aperture_video_memory_f() |
gmmu_new_pte_kind_f(kind_v) |
gmmu_new_pte_comptagline_f(*ctag / SZ_128K);
pte_w[1] = gmmu_new_pte_kind_f(kind_v) |
gmmu_new_pte_comptagline_f(*ctag / SZ_128K);
if (rw_flag == gk20a_mem_flag_read_only)
pte_w[0] |= gmmu_new_pte_read_only_true_f();
if (unmapped_pte && !cacheable)
pte_w[0] |= gmmu_new_pte_read_only_true_f();
else if (!cacheable)
pte_w[1] |= gmmu_new_pte_vol_true_f();
pte_w[0] |= gmmu_new_pte_vol_true_f();
gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d"
" ctag=%d vol=%d"
@@ -289,7 +288,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
*ctag += page_size;
} else if (sparse) {
pte_w[0] = gmmu_new_pte_valid_false_f();
pte_w[1] |= gmmu_new_pte_vol_true_f();
pte_w[0] |= gmmu_new_pte_vol_true_f();
} else {
gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i);
}