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gpu: nvgpu: setup HW for each GR instance

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Get number of SMs from GR instance specific nvgpu_gr_config pointer
instead of global SM count in below functions :
nvgpu_gr_fs_state_init()
gv11b_gr_init_sm_id_config()

Update nvgpu_gr_config_get_gpc_skip_mask() to return 0 in case gpc_index
is greater than available gpc_count. This is not MIG specific, but based
on code review possible even today for existing chips.
See gm20b_gr_init_pd_skip_table_gpc()

Update nvgpu_gr_get_override_ecc_val() to return GR instance specific
value.

Execute gr_init_setup_hw() for each GR instance.

Disable below failing unit tests:
nvgpu_gr_fs_state.test_gr_fs_state_error_injection
nvgpu_gr_init.test_gr_init_hal_config_error_injection

Jira NVGPU-5648

Change-Id: Ie8f1c0c304c634756786d85facf336a5c9ae8195
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2410702
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Deepak Nibade
2020-09-04 10:21:56 +05:30
committed by Alex Waterman
parent 3df2ed4f82
commit bafeea3530
9 changed files with 17 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/common/gr/fs_state.c
View File

@@ -99,6 +99,7 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
u32 max_tpc_cnt;
#endif
u32 gpc_cnt, tpc_cnt;
u32 num_sm;
int err = 0;
nvgpu_log_fn(g, " ");
@@ -110,10 +111,10 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
return err;
}
nvgpu_assert(g->ops.gr.init.get_no_of_sm(g) > 0U);
num_sm = nvgpu_gr_config_get_no_of_sm(config);
nvgpu_assert(num_sm > 0U);
for (sm_id = 0; sm_id < g->ops.gr.init.get_no_of_sm(g);
sm_id++) {
for (sm_id = 0; sm_id < num_sm; sm_id++) {
struct nvgpu_sm_info *sm_info =
nvgpu_gr_config_get_sm_info(config, sm_id);
tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);

8
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -210,7 +210,7 @@ int nvgpu_gr_suspend(struct gk20a *g)
static int gr_init_setup_hw(struct gk20a *g)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = &g->gr[g->mig.cur_gr_instance];
int err;
nvgpu_log_fn(g, " ");
@@ -223,7 +223,6 @@ static int gr_init_setup_hw(struct gk20a *g)
g->ops.gr.init.gpc_mmu(g);
/* load gr floorsweeping registers */
g->ops.gr.init.pes_vsc_stream(g);
#ifdef CONFIG_NVGPU_GRAPHICS
@@ -251,8 +250,6 @@ static int gr_init_setup_hw(struct gk20a *g)
/** Enable TPC exceptions per GPC */
g->ops.gr.intr.enable_gpc_exceptions(g, gr->config);
/** TBD: enable per BE exceptions */
/* enable ECC for L1/SM */
if (g->ops.gr.init.ecc_scrub_reg != NULL) {
err = g->ops.gr.init.ecc_scrub_reg(g, gr->config);
@@ -828,7 +825,8 @@ int nvgpu_gr_init_support(struct gk20a *g)
return err;
}
err = gr_init_setup_hw(g);
err = nvgpu_gr_exec_with_ret_for_each_instance(g,
gr_init_setup_hw(g));
if (err != 0) {
return err;
}

3
drivers/gpu/nvgpu/common/gr/gr_config.c
View File

@@ -762,6 +762,9 @@ void nvgpu_gr_config_set_gpc_tpc_mask(struct nvgpu_gr_config *config,
u32 nvgpu_gr_config_get_gpc_skip_mask(struct nvgpu_gr_config *config,
u32 gpc_index)
{
if (gpc_index >= config->gpc_count) {
return 0;
}
return config->gpc_skip_mask[gpc_index];
}

2
drivers/gpu/nvgpu/common/gr/gr_utils.c
View File

@@ -51,7 +51,7 @@ struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g)
#ifdef CONFIG_NVGPU_NON_FUSA
u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g)
{
return g->gr->fecs_feature_override_ecc_val;
return g->gr[g->mig.cur_gr_instance].fecs_feature_override_ecc_val;
}
void nvgpu_gr_override_ecc_val(struct nvgpu_gr *gr, u32 ecc_val)

2
drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100_fusa.c
View File

@@ -439,7 +439,7 @@ int gv100_gr_config_init_sm_id_table(struct gk20a *g,
goto exit_build_table;
}
gv100_gr_config_set_sminfo(g, gr_config, num_sm,sm_per_tpc,
gv100_gr_config_set_sminfo(g, gr_config, num_sm, sm_per_tpc,
gpc_table, tpc_table);
nvgpu_gr_config_set_no_of_sm(gr_config, num_sm);

2
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
View File

@@ -438,7 +438,7 @@ int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
u32 tpc_index, gpc_index, tpc_id;
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr_config);
u32 tpc_cnt = nvgpu_safe_sub_u32(
nvgpu_gr_config_get_tpc_count(gr_config), 1U);

4
userspace/required_tests.ini
View File

@@ -624,7 +624,7 @@ test_gr_falcon_init_ctxsw.gr_falcon_init_ctxsw=0
test_gr_falcon_query_test.gr_falcon_query_test=0
[nvgpu_gr_fs_state]
test_gr_fs_state_error_injection.gr_fs_state_error_injection=0
test_gr_fs_state_error_injection.gr_fs_state_error_injection=2
test_gr_init_setup_cleanup.gr_fs_state_cleanup=0
test_gr_init_setup_ready.gr_fs_state_setup=0
@@ -637,7 +637,7 @@ test_gr_remove_setup.gr_global_ctx_cleanup=0
[nvgpu_gr_init]
test_gr_init_ecc_features.gr_ecc_features=0
test_gr_init_error_injections.gr_init_error_injections=2
test_gr_init_hal_config_error_injection.gr_init_hal_config_error_injection=0
test_gr_init_hal_config_error_injection.gr_init_hal_config_error_injection=2
test_gr_init_hal_ecc_scrub_reg.gr_init_hal_ecc_scrub_reg=0
test_gr_init_hal_error_injection.gr_init_hal_error_injection=0
test_gr_init_hal_fe_pwr_mode.gr_init_hal_fe_pwr_mode=0

2
userspace/units/gr/fs_state/nvgpu-gr-fs-state.c
View File

@@ -90,7 +90,7 @@ int test_gr_fs_state_error_injection(struct unit_module *m,
struct unit_module_test nvgpu_gr_fs_state_tests[] = {
UNIT_TEST(gr_fs_state_setup, test_gr_init_setup_ready, NULL, 0),
UNIT_TEST(gr_fs_state_error_injection, test_gr_fs_state_error_injection, NULL, 0),
UNIT_TEST(gr_fs_state_error_injection, test_gr_fs_state_error_injection, NULL, 2),
UNIT_TEST(gr_fs_state_cleanup, test_gr_init_setup_cleanup, NULL, 0),
};

2
userspace/units/gr/init/nvgpu-gr-init.c
View File

@@ -561,7 +561,7 @@ struct unit_module_test nvgpu_gr_init_tests[] = {
UNIT_TEST(gr_init_hal_wait_fe_idle, test_gr_init_hal_wait_fe_idle, NULL, 0),
UNIT_TEST(gr_init_hal_fe_pwr_mode, test_gr_init_hal_fe_pwr_mode, NULL, 0),
UNIT_TEST(gr_init_hal_ecc_scrub_reg, test_gr_init_hal_ecc_scrub_reg, NULL, 0),
UNIT_TEST(gr_init_hal_config_error_injection, test_gr_init_hal_config_error_injection, NULL, 0),
UNIT_TEST(gr_init_hal_config_error_injection, test_gr_init_hal_config_error_injection, NULL, 2),
UNIT_TEST(gr_suspend, test_gr_suspend, NULL, 0),
UNIT_TEST(gr_ecc_features, test_gr_init_ecc_features, NULL, 0),
UNIT_TEST(gr_init_error_injections, test_gr_init_error_injections, NULL, 2),