nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: select target based on aperture

Browse Source 
For bar2 and pmu instance blocks, use gk20a_aperture_mask()
to select target address (i.e. if address is in sysmem or
vidmem) based on aperture

Also add target accessors for gr_fecs_new_ctx and
gr_fecs_arb_ctx_ptr

Jira DNVGPU-22

Change-Id: Ieaa80bd83a4191fe57b7fba6e0f9cdaeb195a077
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1216138
(cherry picked from commit 7a9f4175abc5dddf0879215de4637b7b6eb0ab7b)
Reviewed-on: http://git-master/r/1219712
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-09-06 16:13:31 +05:30
parent 5544272474
commit bb6923908a
4 changed files with 41 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/gp106/hw_gr_gp106.h
View File

@@ -1342,6 +1342,14 @@ static inline u32 gr_fecs_new_ctx_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_new_ctx_valid_s(void)
{
return 1;
@@ -1394,6 +1402,14 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_arb_ctx_cmd_r(void)
{
return 0x00409a10;

8
drivers/gpu/nvgpu/gp106/sec2_gp106.c
View File

@@ -169,7 +169,9 @@ int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
pwr_pmu_new_instblk_ptr_f(
gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
pwr_pmu_new_instblk_valid_f(1) |
pwr_pmu_new_instblk_target_sys_coh_f());
gk20a_aperture_mask(g, &mm->pmu.inst_block,
pwr_pmu_new_instblk_target_sys_coh_f(),
pwr_pmu_new_instblk_target_fb_f()));
data = gk20a_readl(g, psec_falcon_debug1_r());
data |= psec_falcon_debug1_ctxsw_mode_m();
@@ -313,7 +315,9 @@ void init_pmu_setup_hw1(struct gk20a *g)
pwr_pmu_new_instblk_ptr_f(
gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
pwr_pmu_new_instblk_valid_f(1) |
pwr_pmu_new_instblk_target_sys_coh_f());
gk20a_aperture_mask(g, &mm->pmu.inst_block,
pwr_pmu_new_instblk_target_sys_coh_f(),
pwr_pmu_new_instblk_target_fb_f()));
/*Copying pmu cmdline args*/
g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,

16
drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
View File

@@ -1414,6 +1414,14 @@ static inline u32 gr_fecs_new_ctx_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_new_ctx_valid_s(void)
{
return 1;
@@ -1466,6 +1474,14 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_arb_ctx_cmd_r(void)
{
return 0x00409a10;

6
drivers/gpu/nvgpu/gp10b/mm_gp10b.c
View File

@@ -105,9 +105,9 @@ static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g)
gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa);
gk20a_writel(g, bus_bar2_block_r(),
(g->mm.vidmem_is_vidmem ?
bus_bar2_block_target_sys_mem_ncoh_f() :
bus_bar2_block_target_vid_mem_f()) |
gk20a_aperture_mask(g, inst_block,
bus_bar2_block_target_sys_mem_ncoh_f(),
bus_bar2_block_target_vid_mem_f()) |
bus_bar2_block_mode_virtual_f() |
bus_bar2_block_ptr_f(inst_pa));