gpu: nvgpu: Fixed out-of-bounds Coverity Defects

Fix following Coverity Defects:
clk_mon_tu104.c : Out-of-bounds read and Out-of-bounds access

CID 10061400
CID 10061401

Bug 3460991

Changed the datatype of domain_mask from u32 to unsigned long
to solve the out-of-bounds defect.

Signed-off-by: Jinesh Parakh <jparakh@nvidia.com>
Change-Id: I1c43bd90053264ee4104ca8c3a33d9ea07f04045
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2708765
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/pmu/clk/clk.c

@@ -60,9 +60,9 @@ static void clk_free_pmupstate(struct gk20a *g)
 	g->pmu->clk_pmu = NULL;
 }
 
-u32 nvgpu_pmu_clk_mon_init_domains(struct gk20a *g)
+unsigned long nvgpu_pmu_clk_mon_init_domains(struct gk20a *g)
 {
-	u32 domain_mask;
+	unsigned long domain_mask;
 
 	(void)g;
 

drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c

@@ -1,7 +1,7 @@
 /*
  * TU104 Clocks Monitor
  *
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -207,7 +207,7 @@ int nvgpu_clk_mon_alloc_memory(struct gk20a *g)
 	return 0;
 }
 
-int tu104_clk_mon_check_status(struct gk20a *g, u32 domain_mask)
+int tu104_clk_mon_check_status(struct gk20a *g, unsigned long domain_mask)
 {
 	u32 reg_address, bit_pos;
 	u32 data;

drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -51,7 +51,7 @@ struct clk_domains_mon_status_params {
 };
 
 bool tu104_clk_mon_check_master_fault_status(struct gk20a *g);
-int tu104_clk_mon_check_status(struct gk20a *g, u32 domain_mask);
+int tu104_clk_mon_check_status(struct gk20a *g, unsigned long domain_mask);
 bool tu104_clk_mon_check_clk_good(struct gk20a *g);
 bool tu104_clk_mon_check_pll_lock(struct gk20a *g);
 

drivers/gpu/nvgpu/include/nvgpu/gops/clk.h

@@ -108,7 +108,7 @@ struct gops_clk {
 	int (*mclk_change)(struct gk20a *g, u16 val);
 	void (*get_change_seq_time)(struct gk20a *g, s64 *change_time);
 	void (*change_host_clk_source)(struct gk20a *g);
-	u32 (*clk_mon_init_domains)(struct gk20a *g);
+	unsigned long (*clk_mon_init_domains)(struct gk20a *g);
 	bool split_rail_support;
 	bool support_pmgr_domain;
 	bool support_lpwr_pg;
@@ -122,7 +122,7 @@ struct gops_clk_mon {
 	int (*clk_mon_alloc_memory)(struct gk20a *g);
 	bool (*clk_mon_check_master_fault_status)(struct gk20a *g);
 	int (*clk_mon_check_status)(struct gk20a *g,
-		u32 domain_mask);
+		unsigned long domain_mask);
 	bool (*clk_mon_check_clk_good)(struct gk20a *g);
 	bool (*clk_mon_check_pll_lock)(struct gk20a *g);
 };

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h

@@ -1,7 +1,7 @@
 /*
  * general clock structures & definitions
  *
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -173,5 +173,5 @@ void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain,
 		u32 *gpcclk_clkmhz,
 		struct nvgpu_clk_slave_freq *vf_point,
 		struct nvgpu_pmu_perf_change_input_clk_info *change_input);
-u32 nvgpu_pmu_clk_mon_init_domains(struct gk20a *g);
+unsigned long nvgpu_pmu_clk_mon_init_domains(struct gk20a *g);
 #endif /* NVGPU_PMU_CLK_H */