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gpu: nvgpu: Restructure boardobjgrpmask unit

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This patch does the following for boardobjgrpmask unit.
1. Remove unused functions and its pointers.
2. Append public functions with nvgpu.
3. Remove unnecessary inclusion of header files.
4. Make local functions as static.
5. Rename function names to increase readibility.
6. Remove boardobj* from static functions.

Jira NVGPU-1977

Change-Id: Ie6d3bd8f55784d29ae4ba720fb3998487ad2b942
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107167
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-04-26 19:04:54 +05:30
committed by mobile promotions
parent 20cd4ce54f
commit bc10ef568e
24 changed files with 263 additions and 444 deletions
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24
drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c
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@@ -51,8 +51,10 @@ DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gv100_get_rate_show, NULL, "%llu\n");
static int sys_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu.clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
/* val = 1 implies CLFC is loaded or enabled */
@@ -78,8 +80,10 @@ DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n");
static int ltc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu.clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
/* val = 1 implies CLFC is loaded or enabled */
@@ -105,8 +109,10 @@ DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n");
static int xbar_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu.clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
/* val = 1 implies CLFC is loaded or enabled */
@@ -133,8 +139,10 @@ DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read,
static int gpc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu.clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
/* val = 1 implies CLFC is loaded or enabled */