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gpu: nvgpu: offset for exterraddr and exterrstat reg

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Compute the offsets for falcon_falcon_exterraddr_r()
and falcon_falcon_exterrstat_r() registers by applying
the mask 0xFFF

JIRA NVGPU-4834

Change-Id: I7cef6f82e7802bea9133f3c95c891de22ef10d07
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2347674
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2020-05-20 18:56:22 +05:30
committed by Alex Waterman
parent bac1bf6061
commit bc4cef7a43
1 changed files with 11 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c
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@@ -556,9 +556,18 @@ void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn)
gk20a_falcon_readl(flcn, falcon_falcon_curctx_r()));
nvgpu_err(g, "falcon_falcon_nxtctx_r : 0x%x",
gk20a_falcon_readl(flcn, falcon_falcon_nxtctx_r()));
/*
* Common Falcon code accesses each engine's falcon registers
* using engine's falcon base address + offset.
* So generate offset for falcon_falcon_exterrstat_r()
* and falcon_falcon_exterraddr_r() registers by applying
* the mask 0xFFF
*/
nvgpu_err(g, "falcon_falcon_exterrstat_r : 0x%x",
gk20a_falcon_readl(flcn, falcon_falcon_exterrstat_r()));
gk20a_falcon_readl(flcn,
(falcon_falcon_exterrstat_r() & 0x0FFF)));
nvgpu_err(g, "falcon_falcon_exterraddr_r : 0x%x",
gk20a_falcon_readl(flcn, falcon_falcon_exterraddr_r()));
gk20a_falcon_readl(flcn,
(falcon_falcon_exterraddr_r() & 0x0FFF)));
}
#endif