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gpu: nvgpu: fix zbc MISRA 10.1 violations

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The gr_gk20a_add_zbc() routine returns a signed error
(errno) status value.

Current callers of this function use a bitwise OR to collect
the returned error status values to generate a single value
to return.

Bitwise OR on signed status values is flagged as a
violation of MISRA Rule 10.1 (not to mention that in this
case it potentially results in a garbage return value).

To eliminate such violations this change modifies the
following routines to fail immediately on the first error
from a call to gr_gk20a_add_zbc():

 * gr_gk20a_load_zbc_default_table()
 * gr_gv11b_load_stencil_default_tbl()

JIRA NVGPU-650

Change-Id: If733c1bb0e05943ff5d0355de729133c89233583
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805501
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2018-08-23 10:55:04 -07:00
committed by mobile promotions
parent cded55940e
commit bc6625b9b2
2 changed files with 48 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -3985,7 +3985,8 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
{
struct zbc_entry zbc_val;
u32 i, err;
u32 i;
int err;
nvgpu_mutex_init(&gr->zbc_lock);
@@ -4001,6 +4002,9 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
zbc_val.color_l2[0] = 0xff000000;
zbc_val.color_ds[3] = 0x3f800000;
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto color_fail;
}
/* Transparent black = (fmt 1 = zero) */
zbc_val.format = gr_ds_zbc_color_fmt_val_zero_v();
@@ -4008,7 +4012,10 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
zbc_val.color_ds[i] = 0;
zbc_val.color_l2[i] = 0;
}
err |= gr_gk20a_add_zbc(g, gr, &zbc_val);
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto color_fail;
}
/* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */
zbc_val.format = gr_ds_zbc_color_fmt_val_unorm_one_v();
@@ -4016,42 +4023,47 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr)
zbc_val.color_ds[i] = 0x3f800000;
zbc_val.color_l2[i] = 0xffffffff;
}
err |= gr_gk20a_add_zbc(g, gr, &zbc_val);
if (!err)
gr->max_default_color_index = 3;
else {
nvgpu_err(g,
"fail to load default zbc color table");
return err;
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto color_fail;
}
gr->max_default_color_index = 3;
/* load default depth table */
zbc_val.type = GK20A_ZBC_TYPE_DEPTH;
zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v();
zbc_val.depth = 0x3f800000;
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto depth_fail;
}
zbc_val.format = gr_ds_zbc_z_fmt_val_fp32_v();
zbc_val.depth = 0;
err |= gr_gk20a_add_zbc(g, gr, &zbc_val);
if (!err)
gr->max_default_depth_index = 2;
else {
nvgpu_err(g,
"fail to load default zbc depth table");
return err;
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto depth_fail;
}
gr->max_default_depth_index = 2;
if (g->ops.gr.load_zbc_s_default_tbl) {
err = g->ops.gr.load_zbc_s_default_tbl(g, gr);
if (err)
if (err != 0) {
return err;
}
}
return 0;
color_fail:
nvgpu_err(g, "fail to load default zbc color table");
return err;
depth_fail:
nvgpu_err(g, "fail to load default zbc depth table");
return err;
}
int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,

27
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1121,7 +1121,7 @@ int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
struct gr_gk20a *gr)
{
struct zbc_entry zbc_val;
u32 err;
int err;
/* load default stencil table */
zbc_val.type = GV11B_ZBC_TYPE_STENCIL;
@@ -1129,23 +1129,30 @@ int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
zbc_val.depth = 0x0;
zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8;
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto fail;
}
zbc_val.depth = 0x1;
zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8;
err |= gr_gk20a_add_zbc(g, gr, &zbc_val);
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto fail;
}
zbc_val.depth = 0xff;
zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8;
err |= gr_gk20a_add_zbc(g, gr, &zbc_val);
if (!err) {
gr->max_default_s_index = 3;
} else {
nvgpu_err(g, "fail to load default zbc stencil table");
return err;
err = gr_gk20a_add_zbc(g, gr, &zbc_val);
if (err != 0) {
goto fail;
}
gr->max_default_s_index = 3;
return 0;
fail:
nvgpu_err(g, "fail to load default zbc stencil table");
return err;
}
int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr)