gpu: nvgpu: add dbg mask bit for vserver

Jira GVSCI-30

Change-Id: I083c301131c7dc37ed272b963ad3d9818e576205
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001192
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Aparna Das
2019-01-22 11:40:28 -08:00
committed by mobile promotions
parent 75e4e7c9bc
commit bccb49d8fb

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -81,6 +81,7 @@ void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
#define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */
#define gpu_dbg_clk_arb BIT(26) /* Clk arbiter debugging. */
#define gpu_dbg_event BIT(27) /* Events to User debugging. */
#define gpu_dbg_vsrv BIT(28) /* server debugging. */
#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */
/**