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gpu: nvgpu: T186 GR FW version update
- pmu version update to sync with CL-19816709 - GPCCS version update to sync with CL-19816709 Change-Id: Ia60bb538ddba35c973183ca2d4d3a7a0013b4b59 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/779628 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Terje Bergstrom
parent
c27e094002
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bda01cda7a
@@ -1976,6 +1976,7 @@ void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base,
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/* Write out the actual data */
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switch (segments->boot_signature) {
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case FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED:
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case FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED:
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case FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED:
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case FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED:
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@@ -324,6 +324,10 @@ struct gk20a_ctxsw_ucode_segments {
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/* sums over the ucode files as sequences of u32, computed to the
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* boot_signature field in the structure above */
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/* T18X FECS remains same as T21X,
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* so FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED used
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* for T18X*/
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#define FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED 0x68edab34
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#define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5c
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#define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78
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#define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b
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@@ -49,7 +49,7 @@
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/* Mapping between AP_CTRLs and Idle counters */
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#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
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#define APP_VERSION_T186_0 19494277
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#define APP_VERSION_T186_0 19816464
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#define APP_VERSION_GM20B_4 19008461
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#define APP_VERSION_GM20B_3 18935575
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#define APP_VERSION_GM20B_2 18694072
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