gpu: nvgpu: T186 GR FW version update

- pmu version update to sync with CL-19816709
- GPCCS version update to sync with CL-19816709

Change-Id: Ia60bb538ddba35c973183ca2d4d3a7a0013b4b59
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/779628
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2015-08-06 12:00:28 +05:30
committed by Terje Bergstrom
parent c27e094002
commit bda01cda7a
3 changed files with 6 additions and 1 deletions

View File

@@ -1976,6 +1976,7 @@ void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base,
/* Write out the actual data */ /* Write out the actual data */
switch (segments->boot_signature) { switch (segments->boot_signature) {
case FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED:
case FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED: case FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED:
case FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED: case FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED:
case FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED: case FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED:

View File

@@ -324,6 +324,10 @@ struct gk20a_ctxsw_ucode_segments {
/* sums over the ucode files as sequences of u32, computed to the /* sums over the ucode files as sequences of u32, computed to the
* boot_signature field in the structure above */ * boot_signature field in the structure above */
/* T18X FECS remains same as T21X,
* so FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED used
* for T18X*/
#define FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED 0x68edab34
#define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5c #define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5c
#define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78 #define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78
#define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b #define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b

View File

@@ -49,7 +49,7 @@
/* Mapping between AP_CTRLs and Idle counters */ /* Mapping between AP_CTRLs and Idle counters */
#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
#define APP_VERSION_T186_0 19494277 #define APP_VERSION_T186_0 19816464
#define APP_VERSION_GM20B_4 19008461 #define APP_VERSION_GM20B_4 19008461
#define APP_VERSION_GM20B_3 18935575 #define APP_VERSION_GM20B_3 18935575
#define APP_VERSION_GM20B_2 18694072 #define APP_VERSION_GM20B_2 18694072