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gpu:nvgpu: Move nvgpu_clk_pmupstate into nvgpu_pmu

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Moved nvgpu_clk_pmupstate structure from gk20a to
nvgpu_pmu.The aim is to have single pmu structure inside
gk20a, that is "nvgpu_pmu" struct and all the global
structures of all units in PMU should be included in
"nvgpu_pmu" struct.

NVGPU-3220

Change-Id: I531aab568a692c55e640ca2c33aa7508b83a9593
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104129
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2019-04-24 15:06:35 +05:30
committed by mobile promotions
parent a4357b0354
commit be0eabeb6c
17 changed files with 156 additions and 149 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/clk_arb/clk_arb.c
View File

@@ -233,7 +233,7 @@ static void nvgpu_clk_arb_run_vf_table_cb(struct nvgpu_clk_arb *arb)
int err;
/* get latest vf curve from pmu */
err = g->clk_pmu->nvgpu_clk_vf_point_cache(g);
err = g->pmu.clk_pmu->nvgpu_clk_vf_point_cache(g);
if (err != 0) {
nvgpu_err(g, "failed to cache VF table");
nvgpu_clk_arb_set_global_alarm(g,

2
drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c
View File

@@ -59,7 +59,7 @@ int gv100_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
{
u32 clkwhich;
struct clk_set_info *p0_info;
struct nvgpu_avfsfllobjs *pfllobjs = g->clk_pmu->avfs_fllobjs;
struct nvgpu_avfsfllobjs *pfllobjs = g->pmu.clk_pmu->avfs_fllobjs;
u16 limit_min_mhz;
bool error_status = false;

34
drivers/gpu/nvgpu/common/pmu/clk/clk.c
View File

@@ -188,31 +188,31 @@ int nvgpu_clk_set_fll_clks(struct gk20a *g,
int status = -EINVAL;
/*set regime ids */
status = g->clk_pmu->get_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK,
status = g->pmu.clk_pmu->get_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK,
&setfllclk->current_regime_id_gpc);
if (status != 0) {
goto done;
}
setfllclk->target_regime_id_gpc = g->clk_pmu->find_regime_id(g,
setfllclk->target_regime_id_gpc = g->pmu.clk_pmu->find_regime_id(g,
CTRL_CLK_DOMAIN_GPCCLK, setfllclk->gpc2clkmhz);
status = g->clk_pmu->get_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK,
status = g->pmu.clk_pmu->get_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK,
&setfllclk->current_regime_id_sys);
if (status != 0) {
goto done;
}
setfllclk->target_regime_id_sys = g->clk_pmu->find_regime_id(g,
setfllclk->target_regime_id_sys = g->pmu.clk_pmu->find_regime_id(g,
CTRL_CLK_DOMAIN_SYSCLK, setfllclk->sys2clkmhz);
status = g->clk_pmu->get_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK,
status = g->pmu.clk_pmu->get_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK,
&setfllclk->current_regime_id_xbar);
if (status != 0) {
goto done;
}
setfllclk->target_regime_id_xbar = g->clk_pmu->find_regime_id(g,
setfllclk->target_regime_id_xbar = g->pmu.clk_pmu->find_regime_id(g,
CTRL_CLK_DOMAIN_XBARCLK, setfllclk->xbar2clkmhz);
status = clk_pmu_vf_inject(g, setfllclk);
@@ -222,19 +222,19 @@ int nvgpu_clk_set_fll_clks(struct gk20a *g,
}
/* save regime ids */
status = g->clk_pmu->set_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK,
status = g->pmu.clk_pmu->set_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK,
setfllclk->target_regime_id_xbar);
if (status != 0) {
goto done;
}
status = g->clk_pmu->set_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK,
status = g->pmu.clk_pmu->set_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK,
setfllclk->target_regime_id_gpc);
if (status != 0) {
goto done;
}
status = g->clk_pmu->set_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK,
status = g->pmu.clk_pmu->set_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK,
setfllclk->target_regime_id_sys);
if (status != 0) {
goto done;
@@ -247,7 +247,7 @@ int nvgpu_clk_get_fll_clks(struct gk20a *g,
struct nvgpu_set_fll_clk *setfllclk)
{
int status = -EINVAL;
status = g->clk_pmu->get_fll(g, setfllclk);
status = g->pmu.clk_pmu->get_fll(g, setfllclk);
return status;
}
@@ -255,7 +255,7 @@ int nvgpu_clk_get_fll_clks(struct gk20a *g,
int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
{
int status = -EINVAL;
status = g->clk_pmu->set_boot_fll(g);
status = g->pmu.clk_pmu->set_boot_fll(g);
return status;
}
@@ -263,12 +263,12 @@ int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
int nvgpu_clk_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu != NULL) {
if (g->pmu.clk_pmu != NULL) {
return 0;
}
g->clk_pmu = nvgpu_kzalloc(g, sizeof(*g->clk_pmu));
if (g->clk_pmu == NULL) {
g->pmu.clk_pmu = nvgpu_kzalloc(g, sizeof(*g->pmu.clk_pmu));
if (g->pmu.clk_pmu == NULL) {
return -ENOMEM;
}
@@ -277,8 +277,8 @@ int nvgpu_clk_init_pmupstate(struct gk20a *g)
void nvgpu_clk_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu);
g->clk_pmu = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu);
g->pmu.clk_pmu = NULL;
}
int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g,
@@ -295,7 +295,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g,
(void) memset(&change_input, 0,
sizeof(struct ctrl_perf_change_seq_change_input));
g->clk_pmu->set_p0_clks(g, &gpcclk_domain, &gpcclk_clkmhz,
g->pmu.clk_pmu->set_p0_clks(g, &gpcclk_domain, &gpcclk_clkmhz,
vf_point, &change_input);
change_input.pstate_index = 0U;

47
drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
View File

@@ -231,7 +231,7 @@ int nvgpu_clk_domain_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e32(g,
&g->clk_pmu->clk_domainobjs->super);
&g->pmu.clk_pmu->clk_domainobjs->super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, status - 0x%x",
@@ -239,8 +239,8 @@ int nvgpu_clk_domain_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu->clk_domainobjs->super.super;
pclkdomainobjs = g->clk_pmu->clk_domainobjs;
pboardobjgrp = &g->pmu.clk_pmu->clk_domainobjs->super.super;
pclkdomainobjs = g->pmu.clk_pmu->clk_domainobjs;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_DOMAIN);
@@ -311,7 +311,8 @@ int nvgpu_clk_domain_sw_setup(struct gk20a *g)
(struct clk_domain_35_slave *)pdomain;
pdomain_master_35 = (struct clk_domain_35_master *)
(void *)
(g->clk_pmu->clk_get_clk_domain((g->clk_pmu),
(g->pmu.clk_pmu->clk_get_clk_domain(
(g->pmu.clk_pmu),
pdomain_slave_35->slave.master_idx));
pdomain_master_35->master.slave_idxs_mask |= BIT32(i);
pdomain_slave_35->super.clk_pos =
@@ -340,7 +341,7 @@ int nvgpu_clk_domain_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu->clk_domainobjs->super.super;
pboardobjgrp = &g->pmu.clk_pmu->clk_domainobjs->super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -717,7 +718,7 @@ static int clkdomaingetslaveclk(struct gk20a *g,
}
slaveidx = BOARDOBJ_GET_IDX(pdomain);
p35master = (struct clk_domain_35_master *)(void *)
g->clk_pmu->clk_get_clk_domain(pclk,
g->pmu.clk_pmu->clk_get_clk_domain(pclk,
((struct clk_domain_35_slave *)pdomain)->slave.master_idx);
pprog = CLK_CLK_PROG_GET(pclk, p35master->
master.super.clk_prog_idx_first);
@@ -766,7 +767,7 @@ static int clkdomainvfsearch(struct gk20a *g,
slaveidx = BOARDOBJ_GET_IDX(pdomain);
pslaveidx = &slaveidx;
p3xmaster = (struct clk_domain_3x_master *)(void *)
g->clk_pmu->clk_get_clk_domain(pclk,
g->pmu.clk_pmu->clk_get_clk_domain(pclk,
((struct clk_domain_3x_slave *)
pdomain)->master_idx);
}
@@ -892,7 +893,7 @@ static int clk_domain_pmudatainit_35_prog(struct gk20a *g,
struct clk_domain_35_prog *pclk_domain_35_prog;
struct clk_domain_3x_prog *pclk_domain_3x_prog;
struct nv_pmu_clk_clk_domain_35_prog_boardobj_set *pset;
struct nvgpu_clk_domains *pdomains = g->clk_pmu->clk_domainobjs;
struct nvgpu_clk_domains *pdomains = g->pmu.clk_pmu->clk_domainobjs;
nvgpu_log_info(g, " ");
@@ -1375,7 +1376,7 @@ static int clk_get_fll_clks_per_clk_domain(struct gk20a *g,
int status = -EINVAL;
struct nvgpu_clk_domain *pdomain;
u8 i;
struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
struct nvgpu_clk_pmupstate *pclk = g->pmu.clk_pmu;
unsigned long bit;
u16 clkmhz = 0;
struct clk_domain_35_master *p35master;
@@ -1402,7 +1403,7 @@ static int clk_get_fll_clks_per_clk_domain(struct gk20a *g,
i = (u8)bit;
p35slave = (struct clk_domain_35_slave *)
(void *)
g->clk_pmu->clk_get_clk_domain(pclk, i);
g->pmu.clk_pmu->clk_get_clk_domain(pclk, i);
clkmhz = 0;
status = p35slave->
@@ -1452,7 +1453,7 @@ static int clk_set_boot_fll_clks_per_clk_domain(struct gk20a *g)
(void) memset(&change_input, 0,
sizeof(struct ctrl_perf_change_seq_change_input));
BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs->super.super),
BOARDOBJGRP_FOR_EACH(&(g->pmu.clk_pmu->clk_domainobjs->super.super),
struct nvgpu_clk_domain *, pclk_domain, i) {
p0_clk_set_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g,
@@ -1534,7 +1535,7 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain,
u16 max_ratio;
u8 i = 0;
BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs->super.super),
BOARDOBJGRP_FOR_EACH(&(g->pmu.clk_pmu->clk_domainobjs->super.super),
struct nvgpu_clk_domain *, pclk_domain, i) {
switch (pclk_domain->api_domain) {
@@ -1673,25 +1674,25 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain,
int nvgpu_clk_domain_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu->clk_domainobjs != NULL) {
if (g->pmu.clk_pmu->clk_domainobjs != NULL) {
return 0;
}
g->clk_pmu->clk_domainobjs = nvgpu_kzalloc(g,
sizeof(*g->clk_pmu->clk_domainobjs));
if (g->clk_pmu->clk_domainobjs == NULL) {
g->pmu.clk_pmu->clk_domainobjs = nvgpu_kzalloc(g,
sizeof(*g->pmu.clk_pmu->clk_domainobjs));
if (g->pmu.clk_pmu->clk_domainobjs == NULL) {
return -ENOMEM;
}
g->clk_pmu->get_fll =
g->pmu.clk_pmu->get_fll =
clk_get_fll_clks_per_clk_domain;
g->clk_pmu->set_boot_fll =
g->pmu.clk_pmu->set_boot_fll =
clk_set_boot_fll_clks_per_clk_domain;
g->clk_pmu->set_p0_clks =
g->pmu.clk_pmu->set_p0_clks =
clk_set_p0_clk_per_domain;
g->clk_pmu->clk_get_clk_domain =
g->pmu.clk_pmu->clk_get_clk_domain =
clk_get_clk_domain_from_index;
g->clk_pmu->clk_domain_clk_prog_link =
g->pmu.clk_pmu->clk_domain_clk_prog_link =
clk_domain_clk_prog_link;
return 0;
@@ -1699,7 +1700,7 @@ int nvgpu_clk_domain_init_pmupstate(struct gk20a *g)
void nvgpu_clk_domain_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu->clk_domainobjs);
g->clk_pmu->clk_domainobjs = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu->clk_domainobjs);
g->pmu.clk_pmu->clk_domainobjs = NULL;
}

47
drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
View File

@@ -148,14 +148,15 @@ int nvgpu_clk_fll_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e32(g, &g->clk_pmu->avfs_fllobjs->super);
status = boardobjgrpconstruct_e32(g,
&g->pmu.clk_pmu->avfs_fllobjs->super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for fll, status - 0x%x", status);
goto done;
}
pfllobjs = g->clk_pmu->avfs_fllobjs;
pboardobjgrp = &(g->clk_pmu->avfs_fllobjs->super.super);
pfllobjs = g->pmu.clk_pmu->avfs_fllobjs;
pboardobjgrp = &(g->pmu.clk_pmu->avfs_fllobjs->super.super);
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, FLL_DEVICE);
@@ -185,7 +186,7 @@ int nvgpu_clk_fll_sw_setup(struct gk20a *g)
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->clk_pmu->avfs_fllobjs->super.super,
&g->pmu.clk_pmu->avfs_fllobjs->super.super,
clk, CLK, clk_fll_device, CLK_FLL_DEVICE);
if (status != 0) {
nvgpu_err(g,
@@ -237,7 +238,7 @@ int nvgpu_clk_fll_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu->avfs_fllobjs->super.super;
pboardobjgrp = &g->pmu.clk_pmu->avfs_fllobjs->super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -264,7 +265,7 @@ static int devinit_get_fll_device_table(struct gk20a *g,
struct nvgpu_vin_device *pvin_dev;
u32 desctablesize;
u32 vbios_domain = NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP;
struct nvgpu_avfsvinobjs *pvinobjs = g->clk_pmu->avfs_vinobjs;
struct nvgpu_avfsvinobjs *pvinobjs = g->pmu.clk_pmu->avfs_vinobjs;
nvgpu_log_info(g, " ");
@@ -314,7 +315,7 @@ static int devinit_get_fll_device_table(struct gk20a *g,
if ((u8)fll_desc_table_entry.vin_idx_logic !=
CTRL_CLK_VIN_ID_UNDEFINED) {
pvin_dev = g->clk_pmu->clk_get_vin(pvinobjs,
pvin_dev = g->pmu.clk_pmu->clk_get_vin(pvinobjs,
(u8)fll_desc_table_entry.vin_idx_logic);
if (pvin_dev == NULL) {
return -EINVAL;
@@ -333,7 +334,7 @@ static int devinit_get_fll_device_table(struct gk20a *g,
if ((u8)fll_desc_table_entry.vin_idx_sram !=
CTRL_CLK_VIN_ID_UNDEFINED) {
pvin_dev = g->clk_pmu->clk_get_vin(pvinobjs,
pvin_dev = g->pmu.clk_pmu->clk_get_vin(pvinobjs,
(u8)fll_desc_table_entry.vin_idx_sram);
if (pvin_dev == NULL) {
return -EINVAL;
@@ -532,7 +533,7 @@ static u8 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz)
{
struct fll_device *pflldev;
u8 j;
struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
struct nvgpu_clk_pmupstate *pclk = g->pmu.clk_pmu;
BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs->super.super),
struct fll_device *, pflldev, j) {
@@ -552,7 +553,7 @@ static int set_regime_id(struct gk20a *g, u32 domain, u8 regimeid)
{
struct fll_device *pflldev;
u8 j;
struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
struct nvgpu_clk_pmupstate *pclk = g->pmu.clk_pmu;
BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs->super.super),
struct fll_device *, pflldev, j) {
@@ -568,7 +569,7 @@ static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid)
{
struct fll_device *pflldev;
u8 j;
struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
struct nvgpu_clk_pmupstate *pclk = g->pmu.clk_pmu;
BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs->super.super),
struct fll_device *, pflldev, j) {
@@ -583,24 +584,24 @@ static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid)
int nvgpu_clk_fll_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu->avfs_fllobjs != NULL) {
if (g->pmu.clk_pmu->avfs_fllobjs != NULL) {
return 0;
}
g->clk_pmu->avfs_fllobjs = nvgpu_kzalloc(g,
sizeof(*g->clk_pmu->avfs_fllobjs));
if (g->clk_pmu->avfs_fllobjs == NULL) {
g->pmu.clk_pmu->avfs_fllobjs = nvgpu_kzalloc(g,
sizeof(*g->pmu.clk_pmu->avfs_fllobjs));
if (g->pmu.clk_pmu->avfs_fllobjs == NULL) {
return -ENOMEM;
}
g->clk_pmu->find_regime_id = find_regime_id;
g->clk_pmu->get_regime_id = get_regime_id;
g->clk_pmu->set_regime_id = set_regime_id;
g->clk_pmu->get_fll_lut_vf_num_entries =
g->pmu.clk_pmu->find_regime_id = find_regime_id;
g->pmu.clk_pmu->get_regime_id = get_regime_id;
g->pmu.clk_pmu->set_regime_id = set_regime_id;
g->pmu.clk_pmu->get_fll_lut_vf_num_entries =
clk_get_fll_lut_vf_num_entries;
g->clk_pmu->get_fll_lut_min_volt =
g->pmu.clk_pmu->get_fll_lut_min_volt =
clk_get_fll_lut_min_volt;
g->clk_pmu->get_fll_lut_step_size =
g->pmu.clk_pmu->get_fll_lut_step_size =
clk_get_fll_lut_step_size;
return 0;
@@ -608,6 +609,6 @@ int nvgpu_clk_fll_init_pmupstate(struct gk20a *g)
void nvgpu_clk_fll_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu->avfs_fllobjs);
g->clk_pmu->avfs_fllobjs = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu->avfs_fllobjs);
g->pmu.clk_pmu->avfs_fllobjs = NULL;
}

25
drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
View File

@@ -269,7 +269,8 @@ static int clk_get_freq_controller_table(struct gk20a *g,
BIOS_GET_FIELD(u8, entry.param0,
NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID);
pclk_domain = g->clk_pmu->clk_get_clk_domain((g->clk_pmu),
pclk_domain = g->pmu.clk_pmu->clk_get_clk_domain(
(g->pmu.clk_pmu),
(u32)entry.clk_domain_idx);
freq_controller_data.freq_controller.clk_domain =
pclk_domain->api_domain;
@@ -361,7 +362,7 @@ int nvgpu_clk_freq_controller_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu->clk_freq_controllers->super.super;
pboardobjgrp = &g->pmu.clk_pmu->clk_freq_controllers->super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -425,7 +426,7 @@ int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g)
int status = 0;
struct boardobjgrp *pboardobjgrp = NULL;
struct nvgpu_clk_freq_controllers *pclk_freq_controllers;
struct nvgpu_avfsfllobjs *pfllobjs = g->clk_pmu->avfs_fllobjs;
struct nvgpu_avfsfllobjs *pfllobjs = g->pmu.clk_pmu->avfs_fllobjs;
struct fll_device *pfll;
struct clk_freq_controller *pclkfreqctrl;
u8 i;
@@ -433,7 +434,7 @@ int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pclk_freq_controllers = g->clk_pmu->clk_freq_controllers;
pclk_freq_controllers = g->pmu.clk_pmu->clk_freq_controllers;
status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super);
if (status != 0) {
nvgpu_err(g,
@@ -442,7 +443,7 @@ int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu->clk_freq_controllers->super.super;
pboardobjgrp = &g->pmu.clk_pmu->clk_freq_controllers->super.super;
pboardobjgrp->pmudatainit = _clk_freq_controllers_pmudatainit;
pboardobjgrp->pmudatainstget =
@@ -507,7 +508,7 @@ int nvgpu_clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
(void) memset(&handler, 0, sizeof(
struct clk_freq_ctlr_rpc_pmucmdhandler_params));
pclk_freq_controllers = g->clk_pmu->clk_freq_controllers;
pclk_freq_controllers = g->pmu.clk_pmu->clk_freq_controllers;
rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
clkload = &rpccall.params.clk_load;
clkload->feature = NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER;
@@ -597,13 +598,13 @@ done:
int nvgpu_clk_freq_controller_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu->clk_freq_controllers != NULL) {
if (g->pmu.clk_pmu->clk_freq_controllers != NULL) {
return 0;
}
g->clk_pmu->clk_freq_controllers = nvgpu_kzalloc(g,
sizeof(*g->clk_pmu->clk_freq_controllers));
if (g->clk_pmu->clk_freq_controllers == NULL) {
g->pmu.clk_pmu->clk_freq_controllers = nvgpu_kzalloc(g,
sizeof(*g->pmu.clk_pmu->clk_freq_controllers));
if (g->pmu.clk_pmu->clk_freq_controllers == NULL) {
return -ENOMEM;
}
@@ -612,6 +613,6 @@ int nvgpu_clk_freq_controller_init_pmupstate(struct gk20a *g)
void nvgpu_clk_freq_controller_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu->clk_freq_controllers);
g->clk_pmu->clk_freq_controllers = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu->clk_freq_controllers);
g->pmu.clk_pmu->clk_freq_controllers = NULL;
}

20
drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c
View File

@@ -154,11 +154,11 @@ int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g)
nvgpu_assert(tmp_num_of_domains <= U8_MAX);
num_of_domains = (u8)tmp_num_of_domains;
pboardobjgrp = &g->clk_pmu->freq_domain_grp_objs->super.super;
pfreq_domain_grp = g->clk_pmu->freq_domain_grp_objs;
pboardobjgrp = &g->pmu.clk_pmu->freq_domain_grp_objs->super.super;
pfreq_domain_grp = g->pmu.clk_pmu->freq_domain_grp_objs;
status = boardobjgrpconstruct_e32(g,
&g->clk_pmu->freq_domain_grp_objs->super);
&g->pmu.clk_pmu->freq_domain_grp_objs->super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk freq domain, status - 0x%x",
@@ -225,7 +225,7 @@ int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g)
nvgpu_log_fn(g, " ");
pboardobjgrp = &g->clk_pmu->freq_domain_grp_objs->super.super;
pboardobjgrp = &g->pmu.clk_pmu->freq_domain_grp_objs->super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -240,13 +240,13 @@ int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g)
int nvgpu_clk_freq_domain_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu->freq_domain_grp_objs != NULL) {
if (g->pmu.clk_pmu->freq_domain_grp_objs != NULL) {
return 0;
}
g->clk_pmu->freq_domain_grp_objs = nvgpu_kzalloc(g,
sizeof(*g->clk_pmu->freq_domain_grp_objs));
if (g->clk_pmu->freq_domain_grp_objs == NULL) {
g->pmu.clk_pmu->freq_domain_grp_objs = nvgpu_kzalloc(g,
sizeof(*g->pmu.clk_pmu->freq_domain_grp_objs));
if (g->pmu.clk_pmu->freq_domain_grp_objs == NULL) {
return -ENOMEM;
}
@@ -255,6 +255,6 @@ int nvgpu_clk_freq_domain_init_pmupstate(struct gk20a *g)
void nvgpu_clk_freq_domain_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu->freq_domain_grp_objs);
g->clk_pmu->freq_domain_grp_objs = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu->freq_domain_grp_objs);
g->pmu.clk_pmu->freq_domain_grp_objs = NULL;
}

46
drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
View File

@@ -115,7 +115,8 @@ int nvgpu_clk_prog_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e255(g, &g->clk_pmu->clk_progobjs->super);
status = boardobjgrpconstruct_e255(g,
&g->pmu.clk_pmu->clk_progobjs->super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk prog, status - 0x%x",
@@ -123,8 +124,8 @@ int nvgpu_clk_prog_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu->clk_progobjs->super.super;
pclkprogobjs = g->clk_pmu->clk_progobjs;
pboardobjgrp = &g->pmu.clk_pmu->clk_progobjs->super.super;
pclkprogobjs = g->pmu.clk_pmu->clk_progobjs;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_PROG);
@@ -146,7 +147,7 @@ int nvgpu_clk_prog_sw_setup(struct gk20a *g)
goto done;
}
status = g->clk_pmu->clk_domain_clk_prog_link(g, g->clk_pmu);
status = g->pmu.clk_pmu->clk_domain_clk_prog_link(g, g->pmu.clk_pmu);
if (status != 0) {
nvgpu_err(g, "error constructing VF point board objects");
goto done;
@@ -164,7 +165,7 @@ int nvgpu_clk_prog_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu->clk_progobjs->super.super;
pboardobjgrp = &g->pmu.clk_pmu->clk_progobjs->super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -518,7 +519,7 @@ static int clk_prog_pmudatainit_1x_master(struct gk20a *g,
struct clk_prog_1x_master *pclk_prog_1x_master;
struct nv_pmu_clk_clk_prog_1x_master_boardobj_set *pset;
size_t vfsize = sizeof(struct ctrl_clk_clk_prog_1x_master_vf_entry) *
g->clk_pmu->clk_progobjs->vf_entry_count;
g->pmu.clk_pmu->clk_progobjs->vf_entry_count;
nvgpu_log_info(g, " ");
@@ -551,7 +552,7 @@ static int clk_prog_pmudatainit_35_master(struct gk20a *g,
struct nv_pmu_clk_clk_prog_35_master_boardobj_set *pset;
size_t voltrail_sec_vfsize =
sizeof(struct ctrl_clk_clk_prog_35_master_sec_vf_entry_voltrail)
* g->clk_pmu->clk_progobjs->vf_sec_entry_count;
* g->pmu.clk_pmu->clk_progobjs->vf_sec_entry_count;
nvgpu_log_info(g, " ");
@@ -578,7 +579,7 @@ static int clk_prog_pmudatainit_35_master_ratio(struct gk20a *g,
struct clk_prog_35_master_ratio *pclk_prog_35_master_ratio;
struct nv_pmu_clk_clk_prog_35_master_ratio_boardobj_set *pset;
size_t slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu->clk_progobjs->slave_entry_count;
g->pmu.clk_pmu->clk_progobjs->slave_entry_count;
nvgpu_log_info(g, " ");
@@ -609,7 +610,7 @@ static int clk_prog_pmudatainit_35_master_table(struct gk20a *g,
struct nv_pmu_clk_clk_prog_35_master_table_boardobj_set *pset;
size_t slavesize = sizeof(
struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu->clk_progobjs->slave_entry_count;
g->pmu.clk_pmu->clk_progobjs->slave_entry_count;
nvgpu_log_info(g, " ");
@@ -746,7 +747,7 @@ static int clk_prog_construct_1x_master(struct gk20a *g,
(struct clk_prog_1x_master *)pargs;
int status = 0;
size_t vfsize = sizeof(struct ctrl_clk_clk_prog_1x_master_vf_entry) *
g->clk_pmu->clk_progobjs->vf_entry_count;
g->pmu.clk_pmu->clk_progobjs->vf_entry_count;
u8 railidx;
nvgpu_log_info(g, " type - %x", BOARDOBJ_GET_TYPE(pargs));
@@ -783,7 +784,7 @@ static int clk_prog_construct_1x_master(struct gk20a *g,
pclkprog->b_o_c_o_v_enabled = ptmpprog->b_o_c_o_v_enabled;
for (railidx = 0;
railidx < g->clk_pmu->clk_progobjs->vf_entry_count;
railidx < g->pmu.clk_pmu->clk_progobjs->vf_entry_count;
railidx++) {
pclkprog->p_vf_entries[railidx].vf_point_idx_first =
CTRL_CLK_CLK_VF_POINT_IDX_INVALID;
@@ -842,7 +843,7 @@ static int clk_prog_construct_35_master_ratio(struct gk20a *g,
int status = 0;
size_t slavesize = sizeof(
struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) *
g->clk_pmu->clk_progobjs->slave_entry_count;
g->pmu.clk_pmu->clk_progobjs->slave_entry_count;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_35_MASTER_RATIO) {
return -EINVAL;
@@ -885,7 +886,7 @@ static int clk_prog_construct_35_master_table(struct gk20a *g,
int status = 0;
size_t slavesize =
sizeof(struct ctrl_clk_clk_prog_1x_master_table_slave_entry) *
g->clk_pmu->clk_progobjs->slave_entry_count;
g->pmu.clk_pmu->clk_progobjs->slave_entry_count;
nvgpu_log_info(g, "type - %x", BOARDOBJ_GET_TYPE(pargs));
@@ -1036,10 +1037,11 @@ static int vfflatten_prog_1x_master(struct gk20a *g,
break;
case CTRL_CLK_PROG_1X_SOURCE_FLL:
voltage_min_uv = g->clk_pmu->get_fll_lut_min_volt(pclk);
voltage_min_uv =
g->pmu.clk_pmu->get_fll_lut_min_volt(pclk);
voltage_step_size_uv =
g->clk_pmu->get_fll_lut_step_size(pclk);
step_count = g->clk_pmu->
g->pmu.clk_pmu->get_fll_lut_step_size(pclk);
step_count = g->pmu.clk_pmu->
get_fll_lut_vf_num_entries(pclk);
/* FLL sources use a voltage-based VF_POINT.*/
@@ -1357,13 +1359,13 @@ static int getslaveclk_prog_1x_master(struct gk20a *g,
int nvgpu_clk_prog_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu->clk_progobjs != NULL) {
if (g->pmu.clk_pmu->clk_progobjs != NULL) {
return 0;
}
g->clk_pmu->clk_progobjs = nvgpu_kzalloc(g,
sizeof(*g->clk_pmu->clk_progobjs));
if (g->clk_pmu->clk_progobjs == NULL) {
g->pmu.clk_pmu->clk_progobjs = nvgpu_kzalloc(g,
sizeof(*g->pmu.clk_pmu->clk_progobjs));
if (g->pmu.clk_pmu->clk_progobjs == NULL) {
return -ENOMEM;
}
@@ -1372,6 +1374,6 @@ int nvgpu_clk_prog_init_pmupstate(struct gk20a *g)
void nvgpu_clk_prog_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu->clk_progobjs);
g->clk_pmu->clk_progobjs = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu->clk_progobjs);
g->pmu.clk_pmu->clk_progobjs = NULL;
}

28
drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
View File

@@ -131,7 +131,7 @@ int nvgpu_clk_vf_point_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e255(g,
&g->clk_pmu->clk_vf_pointobjs->super);
&g->pmu.clk_pmu->clk_vf_pointobjs->super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk vfpoint, status - 0x%x",
@@ -139,7 +139,7 @@ int nvgpu_clk_vf_point_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu->clk_vf_pointobjs->super.super;
pboardobjgrp = &g->pmu.clk_pmu->clk_vf_pointobjs->super.super;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_VF_POINT);
@@ -153,7 +153,7 @@ int nvgpu_clk_vf_point_sw_setup(struct gk20a *g)
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->clk_pmu->clk_vf_pointobjs->super.super,
&g->pmu.clk_pmu->clk_vf_pointobjs->super.super,
clk, CLK, clk_vf_point, CLK_VF_POINT);
if (status != 0) {
nvgpu_err(g,
@@ -178,7 +178,7 @@ int nvgpu_clk_vf_point_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu->clk_vf_pointobjs->super.super;
pboardobjgrp = &g->pmu.clk_pmu->clk_vf_pointobjs->super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -565,7 +565,7 @@ int nvgpu_clk_vf_point_cache(struct gk20a *g)
u32 ver = g->params.gpu_arch + g->params.gpu_impl;
nvgpu_log_info(g, " ");
pclk_vf_points = g->clk_pmu->clk_vf_pointobjs;
pclk_vf_points = g->pmu.clk_pmu->clk_vf_pointobjs;
pboardobjgrp = &pclk_vf_points->super.super;
pboardobjgrpmask = &pclk_vf_points->super.mask.super;
@@ -594,9 +594,9 @@ int nvgpu_clk_vf_point_cache(struct gk20a *g)
}
} else {
voltage_min_uv = g->clk_pmu->avfs_fllobjs->lut_min_voltage_uv;
voltage_min_uv = g->pmu.clk_pmu->avfs_fllobjs->lut_min_voltage_uv;
voltage_step_size_uv =
g->clk_pmu->avfs_fllobjs->lut_step_size_uv;
g->pmu.clk_pmu->avfs_fllobjs->lut_step_size_uv;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
pclk_vf_point = (struct clk_vf_point *)(void *)pboardobj;
gpcclk_voltuv =
@@ -617,23 +617,23 @@ int nvgpu_clk_vf_point_cache(struct gk20a *g)
int nvgpu_clk_vf_point_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu->clk_vf_pointobjs != NULL) {
if (g->pmu.clk_pmu->clk_vf_pointobjs != NULL) {
return 0;
}
g->clk_pmu->clk_vf_pointobjs = nvgpu_kzalloc(g,
sizeof(*g->clk_pmu->clk_vf_pointobjs));
if (g->clk_pmu->clk_vf_pointobjs == NULL) {
g->pmu.clk_pmu->clk_vf_pointobjs = nvgpu_kzalloc(g,
sizeof(*g->pmu.clk_pmu->clk_vf_pointobjs));
if (g->pmu.clk_pmu->clk_vf_pointobjs == NULL) {
return -ENOMEM;
}
g->clk_pmu->nvgpu_clk_vf_point_cache = nvgpu_clk_vf_point_cache;
g->pmu.clk_pmu->nvgpu_clk_vf_point_cache = nvgpu_clk_vf_point_cache;
return 0;
}
void nvgpu_clk_vf_point_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu->clk_vf_pointobjs);
g->clk_pmu->clk_vf_pointobjs = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu->clk_vf_pointobjs);
g->pmu.clk_pmu->clk_vf_pointobjs = NULL;
}

29
drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
View File

@@ -97,7 +97,7 @@ static int nvgpu_clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
gain = 0;
offset = 0;
pvindev = (struct vin_device_v20 *)(void *)
g->clk_pmu->clk_get_vin(pvinobjs, i);
g->pmu.clk_pmu->clk_get_vin(pvinobjs, i);
status = g->ops.fuse.read_vin_cal_gain_offset_fuse(g,
pvindev->super.id, &gain, &offset);
if (status != 0) {
@@ -185,7 +185,8 @@ int nvgpu_clk_vin_sw_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
status = boardobjgrpconstruct_e32(g, &g->clk_pmu->avfs_vinobjs->super);
status = boardobjgrpconstruct_e32(g,
&g->pmu.clk_pmu->avfs_vinobjs->super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk vin, statu - 0x%x",
@@ -193,8 +194,8 @@ int nvgpu_clk_vin_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &g->clk_pmu->avfs_vinobjs->super.super;
pvinobjs = g->clk_pmu->avfs_vinobjs;
pboardobjgrp = &g->pmu.clk_pmu->avfs_vinobjs->super.super;
pvinobjs = g->pmu.clk_pmu->avfs_vinobjs;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, VIN_DEVICE);
@@ -211,7 +212,7 @@ int nvgpu_clk_vin_sw_setup(struct gk20a *g)
pboardobjgrp->pmudatainstget = _clk_vin_devgrp_pmudata_instget;
pboardobjgrp->pmustatusinstget = _clk_vin_devgrp_pmustatus_instget;
status = devinit_get_vin_device_table(g, g->clk_pmu->avfs_vinobjs);
status = devinit_get_vin_device_table(g, g->pmu.clk_pmu->avfs_vinobjs);
if (status != 0) {
goto done;
}
@@ -220,7 +221,7 @@ int nvgpu_clk_vin_sw_setup(struct gk20a *g)
nvgpu_clk_avfs_get_vin_cal_fuse_v20(g, pvinobjs, pvindev);
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->clk_pmu->avfs_vinobjs->super.super,
&g->pmu.clk_pmu->avfs_vinobjs->super.super,
clk, CLK, clk_vin_device, CLK_VIN_DEVICE);
if (status != 0) {
nvgpu_err(g,
@@ -241,7 +242,7 @@ int nvgpu_clk_vin_pmu_setup(struct gk20a *g)
nvgpu_log_info(g, " ");
pboardobjgrp = &g->clk_pmu->avfs_vinobjs->super.super;
pboardobjgrp = &g->pmu.clk_pmu->avfs_vinobjs->super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
@@ -546,23 +547,23 @@ done:
int nvgpu_clk_vin_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->clk_pmu->avfs_vinobjs != NULL) {
if (g->pmu.clk_pmu->avfs_vinobjs != NULL) {
return 0;
}
g->clk_pmu->avfs_vinobjs = nvgpu_kzalloc(g,
sizeof(*g->clk_pmu->avfs_vinobjs));
if (g->clk_pmu->avfs_vinobjs == NULL) {
g->pmu.clk_pmu->avfs_vinobjs = nvgpu_kzalloc(g,
sizeof(*g->pmu.clk_pmu->avfs_vinobjs));
if (g->pmu.clk_pmu->avfs_vinobjs == NULL) {
return -ENOMEM;
}
g->clk_pmu->clk_get_vin = clk_get_vin_from_index;
g->pmu.clk_pmu->clk_get_vin = clk_get_vin_from_index;
return 0;
}
void nvgpu_clk_vin_free_pmupstate(struct gk20a *g)
{
nvgpu_kfree(g, g->clk_pmu->avfs_vinobjs);
g->clk_pmu->avfs_vinobjs = NULL;
nvgpu_kfree(g, g->pmu.clk_pmu->avfs_vinobjs);
g->pmu.clk_pmu->avfs_vinobjs = NULL;
}

2
drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
View File

@@ -131,7 +131,7 @@ static void build_change_seq_boot (struct gk20a *g)
script_last->buf.change.data.flags = CTRL_PERF_CHANGE_SEQ_CHANGE_NONE;
BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs->super.super),
BOARDOBJGRP_FOR_EACH(&(g->pmu.clk_pmu->clk_domainobjs->super.super),
struct nvgpu_clk_domain *, pdomain, i) {
p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g,

2
drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c
View File

@@ -124,7 +124,7 @@ static int parse_pstate_entry_6x(struct gk20a *g,
clk_domain = (struct nvgpu_clk_domain *)
BOARDOBJGRP_OBJ_GET_BY_IDX(
&g->clk_pmu->clk_domainobjs->super.super, clkidx);
&g->pmu.clk_pmu->clk_domainobjs->super.super, clkidx);
pclksetinfo = &pstate->clklist.clksetinfo[clkidx];
clk_entry = (struct vbios_pstate_entry_clock_6x *)p;

2
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
View File

@@ -776,7 +776,7 @@ int nvgpu_vfe_get_freq_margin_limit(struct gk20a *g, u32 *fmargin_mhz)
struct nv_pmu_rpc_struct_perf_vfe_eval rpc;
int status = 0;
u8 fmargin_idx;
struct nvgpu_avfsfllobjs *pfllobjs = g->clk_pmu->avfs_fllobjs;
struct nvgpu_avfsfllobjs *pfllobjs = g->pmu.clk_pmu->avfs_fllobjs;
fmargin_idx = pfllobjs->freq_margin_vfe_idx;
if (fmargin_idx == 255U) {

2
drivers/gpu/nvgpu/hal/clk/clk_gv100.c
View File

@@ -214,7 +214,7 @@ int gv100_clk_domain_get_f_points(
int status = -EINVAL;
struct nvgpu_clk_domain *pdomain;
u8 i;
struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
struct nvgpu_clk_pmupstate *pclk = g->pmu.clk_pmu;
if (pfpointscount == NULL) {
return -EINVAL;
}

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -51,7 +51,6 @@ struct nvgpu_gpu_ctxsw_trace_filter;
#endif
struct priv_cmd_entry;
struct nvgpu_setup_bind_args;
struct nvgpu_clk_pmupstate;
struct perf_pmupstate;
struct boardobjgrp;
struct boardobjgrp_pmu_cmd;
@@ -1971,7 +1970,6 @@ struct gk20a {
struct nvgpu_pmu pmu;
struct nvgpu_acr *acr;
struct nvgpu_ecc ecc;
struct nvgpu_clk_pmupstate *clk_pmu;
struct perf_pmupstate *perf_pmu;
struct pmgr_pmupstate *pmgr_pmu;
struct therm_pmupstate *therm_pmu;

3
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -41,6 +41,8 @@
#define nvgpu_pmu_dbg(g, fmt, args...) \
nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
struct nvgpu_clk_pmupstate;
/* defined by pmu hw spec */
#define GK20A_PMU_VA_SIZE (512U * 1024U * 1024U)
#define GK20A_PMU_UCODE_SIZE_MAX (256U * 1024U)
@@ -158,6 +160,7 @@ struct nvgpu_pmu {
struct nvgpu_pmu_pg *pg;
struct nvgpu_pmu_perfmon *pmu_perfmon;
struct nvgpu_clk_pmupstate *clk_pmu;
void (*remove_support)(struct nvgpu_pmu *pmu);
void (*volt_rpc_handler)(struct gk20a *g,

12
drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c
View File

@@ -52,7 +52,7 @@ static int sys_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
/* val = 1 implies CLFC is loaded or enabled */
@@ -79,7 +79,7 @@ static int ltc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
/* val = 1 implies CLFC is loaded or enabled */
@@ -106,7 +106,7 @@ static int xbar_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
/* val = 1 implies CLFC is loaded or enabled */
@@ -134,7 +134,7 @@ static int gpc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = boardobjgrpmask_bitget(
&g->clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
&g->pmu.clk_pmu->clk_freq_controllers->freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
/* val = 1 implies CLFC is loaded or enabled */
@@ -165,8 +165,8 @@ static int vftable_show(struct seq_file *s, void *unused)
u32 voltage_min_uv, voltage_step_size_uv;
u32 gpcclk_clkmhz = 0, gpcclk_voltuv = 0;
voltage_min_uv = g->clk_pmu->avfs_fllobjs->lut_min_voltage_uv;
voltage_step_size_uv = g->clk_pmu->avfs_fllobjs->lut_step_size_uv;
voltage_min_uv = g->pmu.clk_pmu->avfs_fllobjs->lut_min_voltage_uv;
voltage_step_size_uv = g->pmu.clk_pmu->avfs_fllobjs->lut_step_size_uv;
for (index = 0; index < CTRL_CLK_LUT_NUM_ENTRIES_GV10x; index++) {
gpcclk_voltuv = voltage_min_uv + index * voltage_step_size_uv;