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gpu: nvgpu: add accessors for runlist ram entry

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Add accessors to modify contents of runlist ram (RAMRL) entry.
Using these accessors we can modify a runlist entry to specify
it as regular channel or TSG entry

Bug 1470692

Change-Id: If39759941ecb07af11152dbddb6fb5a67c14b26e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/416611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Randy Spurlock <rspurlock@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2014-05-28 19:41:13 +05:30
committed by Dan Willemsen
parent e6eb4b59f6
commit bea937a74e
1 changed files with 41 additions and 1 deletions
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42
drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -386,4 +386,44 @@ static inline u32 ram_rl_entry_size_v(void)
{
return 0x00000008;
}
static inline u32 ram_rl_entry_chid_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 ram_rl_entry_id_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 ram_rl_entry_type_f(u32 v)
{
return (v & 0x1) << 13;
}
static inline u32 ram_rl_entry_type_chid_f(void)
{
return 0x0;
}
static inline u32 ram_rl_entry_type_tsg_f(void)
{
return 0x2000;
}
static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
{
return (v & 0xf) << 14;
}
static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
{
return 0xc000;
}
static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
{
return (v & 0xff) << 18;
}
static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
{
return 0x2000000;
}
static inline u32 ram_rl_entry_tsg_length_f(u32 v)
{
return (v & 0x3f) << 26;
}
#endif