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gpu: nvgpu: obj_ctx: fix CERT-C INT violations

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Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:310:
cert_violation: Casting "size" from "unsigned long" to "unsigned int"
 without checking its value may result in lost or misinterpreted data.

Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:594:
cert_violation: Unsigned integer operation
 "(*g->ops.gr.init.get_patch_slots)(g, config) * 2U" may wrap.

JIRA NVGPU-3410

Change-Id: Icae8246903693d7f5ad66635d3e81d22f6ff2df5
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118522
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nitin Kumbhar
2019-05-14 14:03:45 +05:30
committed by mobile promotions
parent 7c5316c142
commit bf03ffbb05
1 changed files with 9 additions and 6 deletions
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15
drivers/gpu/nvgpu/common/gr/obj_ctx.c
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@@ -34,6 +34,7 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/fs_state.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/secure_ops.h>
#include "obj_ctx_priv.h"
@@ -283,7 +284,7 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g,
struct nvgpu_gr_config *config, struct nvgpu_gr_ctx *gr_ctx, bool patch)
{
u64 addr;
size_t size;
u32 size;
nvgpu_log_fn(g, " ");
@@ -297,15 +298,16 @@ int nvgpu_gr_obj_ctx_commit_global_ctx_buffers(struct gk20a *g,
/* global pagepool buffer */
addr = nvgpu_gr_ctx_get_global_ctx_va(gr_ctx, NVGPU_GR_CTX_PAGEPOOL_VA);
size = nvgpu_gr_global_ctx_get_size(global_ctx_buffer,
NVGPU_GR_GLOBAL_CTX_PAGEPOOL);
size = nvgpu_secure_cast_u64_to_u32(nvgpu_gr_global_ctx_get_size(
global_ctx_buffer, NVGPU_GR_GLOBAL_CTX_PAGEPOOL));
g->ops.gr.init.commit_global_pagepool(g, gr_ctx, addr, size, patch,
true);
/* global bundle cb */
addr = nvgpu_gr_ctx_get_global_ctx_va(gr_ctx, NVGPU_GR_CTX_CIRCULAR_VA);
size = g->ops.gr.init.get_bundle_cb_default_size(g);
size = nvgpu_secure_cast_u64_to_u32(
g->ops.gr.init.get_bundle_cb_default_size(g));
g->ops.gr.init.commit_global_bundle_cb(g, gr_ctx, addr, size, patch);
@@ -591,8 +593,9 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
nvgpu_gr_ctx_set_size(gr_ctx_desc,
NVGPU_GR_CTX_PATCH_CTX,
g->ops.gr.init.get_patch_slots(g, config) *
PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY);
nvgpu_secure_mult_u32(
g->ops.gr.init.get_patch_slots(g, config),
PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY));
err = nvgpu_gr_ctx_alloc_patch_ctx(g, gr_ctx, gr_ctx_desc, vm);
if (err != 0) {