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gpu: nvgpu: move gk20a_gr_wait_initialized call

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Move gk20a_gr_wait_initialized function to common.gr.init as
nvgpu_gr_wait_initialized function. Update all the files calling
this function.

JIRA NVGPU-1885

Change-Id: Ic75d3736d9b07a32c2bd07a5d576467352ab93cf
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082946
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-03-27 08:40:38 -07:00
committed by mobile promotions
parent e086c6442d
commit bf485dc68b
8 changed files with 27 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -140,7 +140,7 @@ int nvgpu_gr_init_fs_state(struct gk20a *g)
}
if (g->ops.gr.config.init_sm_id_table != NULL) {
err = g->ops.gr.config.init_sm_id_table(g->gr.config);
err = g->ops.gr.config.init_sm_id_table(gr_config);
if (err != 0) {
return err;
}
@@ -190,3 +190,9 @@ int nvgpu_gr_init_fs_state(struct gk20a *g)
return err;
}
/* Wait until GR is initialized */
void nvgpu_gr_wait_initialized(struct gk20a *g)
{
NVGPU_COND_WAIT(&g->gr.init_wq, g->gr.initialized, 0U);
}

3
drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
View File

@@ -29,6 +29,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
#include <nvgpu/engines.h>
#include <nvgpu/gr/gr.h>
/* state transition :
* OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
@@ -535,7 +536,7 @@ int nvgpu_pmu_init_powergating(struct gk20a *g)
pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g);
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
for (pg_engine_id = PMU_PG_ELPG_ENGINE_ID_GRAPHICS;
pg_engine_id < PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE;

19
drivers/gpu/nvgpu/common/power_features/cg/cg.c
View File

@@ -21,6 +21,7 @@
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/enabled.h>
#include <nvgpu/power_features/cg.h>
@@ -93,7 +94,7 @@ void nvgpu_cg_elcg_enable(struct gk20a *g)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
@@ -110,7 +111,7 @@ void nvgpu_cg_elcg_disable(struct gk20a *g)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
@@ -128,7 +129,7 @@ void nvgpu_cg_blcg_mode_enable(struct gk20a *g)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->blcg_enabled) {
@@ -146,7 +147,7 @@ void nvgpu_cg_blcg_mode_disable(struct gk20a *g)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->blcg_enabled) {
@@ -304,7 +305,7 @@ void nvgpu_cg_slcg_gr_perf_ltc_load_enable(struct gk20a *g)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
@@ -331,7 +332,7 @@ void nvgpu_cg_slcg_gr_perf_ltc_load_disable(struct gk20a *g)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
@@ -475,7 +476,7 @@ void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_release(&g->cg_pg_lock);
if (enable) {
@@ -502,7 +503,7 @@ void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {
@@ -563,7 +564,7 @@ void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
return;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {

7
drivers/gpu/nvgpu/common/power_features/pg/pg.c
View File

@@ -21,6 +21,7 @@
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/pmu.h>
#include <nvgpu/power_features/pg.h>
@@ -46,7 +47,7 @@ int nvgpu_pg_elpg_enable(struct gk20a *g)
return 0;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elpg_enabled) {
@@ -66,7 +67,7 @@ int nvgpu_pg_elpg_disable(struct gk20a *g)
return 0;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elpg_enabled) {
@@ -87,7 +88,7 @@ int nvgpu_pg_elpg_set_elpg_enabled(struct gk20a *g, bool enable)
return 0;
}
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {

5
drivers/gpu/nvgpu/common/power_features/power_features.c
View File

@@ -21,6 +21,7 @@
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/power_features/power_features.h>
@@ -31,7 +32,7 @@ int nvgpu_cg_pg_disable(struct gk20a *g)
nvgpu_log_fn(g, " ");
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
/* disable elpg before clock gating */
err = nvgpu_pg_elpg_disable(g);
@@ -53,7 +54,7 @@ int nvgpu_cg_pg_enable(struct gk20a *g)
nvgpu_log_fn(g, " ");
gk20a_gr_wait_initialized(g);
nvgpu_gr_wait_initialized(g);
nvgpu_cg_elcg_enable(g);

6
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2252,12 +2252,6 @@ int gk20a_init_gr_support(struct gk20a *g)
return 0;
}
/* Wait until GR is initialized */
void gk20a_gr_wait_initialized(struct gk20a *g)
{
NVGPU_COND_WAIT(&g->gr.init_wq, g->gr.initialized, 0U);
}
#define NVA297_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU
#define NVA297_SET_CIRCULAR_BUFFER_SIZE 0x1280U
#define NVA297_SET_SHADER_EXCEPTIONS 0x1528U

1
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -298,7 +298,6 @@ void gk20a_init_gr(struct gk20a *g);
int gk20a_init_gr_support(struct gk20a *g);
int gk20a_enable_gr_hw(struct gk20a *g);
int gk20a_gr_reset(struct gk20a *g);
void gk20a_gr_wait_initialized(struct gk20a *g);
int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a);

1
drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
View File

@@ -32,5 +32,6 @@ int nvgpu_gr_suspend(struct gk20a *g);
void nvgpu_gr_flush_channel_tlb(struct gk20a *g);
u32 nvgpu_gr_get_idle_timeout(struct gk20a *g);
int nvgpu_gr_init_fs_state(struct gk20a *g);
void nvgpu_gr_wait_initialized(struct gk20a *g);
#endif /* NVGPU_GR_H */