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gpu: nvgpu: don't check ch activity on bind

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Delete an unnecessary check of the active_channels bitmap when
attempting to bind a channel to a TSG. There is already a verification
that the channel must not be a part of a TSG; if it's not, it cannot be
set in the bitmap. All channels become active via a parent TSG, but the
activity check predates this design.

A channel is bound to a TSG early before setting up its gpfifo etc. and
mandatory membership of a TSG is one of the setup_bind prechecks.

Jira NVGPU-6425

Change-Id: Id34686f198db0a0265ffd6a49a0b2e47c37fd5f7
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621211
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Konsta Hölttä
2021-11-01 17:38:34 +02:00
committed by mobile promotions
parent 3cf796b787
commit c0473460ea
1 changed files with 0 additions and 23 deletions
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23
drivers/gpu/nvgpu/common/fifo/tsg.c
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@@ -70,24 +70,6 @@ struct nvgpu_tsg *nvgpu_tsg_get_from_id(struct gk20a *g, u32 tsgid)
return &f->tsg[tsgid];
}
static bool nvgpu_tsg_is_channel_active(struct gk20a *g,
struct nvgpu_channel *ch)
{
struct nvgpu_fifo *f = &g->fifo;
struct nvgpu_runlist *runlist;
unsigned int i;
for (i = 0; i < f->num_runlists; ++i) {
runlist = &f->active_runlists[i];
if (nvgpu_test_bit(ch->chid, runlist->domain->active_channels)) {
return true;
}
}
return false;
}
/*
* API to mark channel as part of TSG
*
@@ -106,11 +88,6 @@ int nvgpu_tsg_bind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch)
return -EINVAL;
}
/* channel cannot be bound to TSG if it is already active */
if (nvgpu_tsg_is_channel_active(tsg->g, ch)) {
return -EINVAL;
}
/* cannot bind more channels than MAX channels supported per TSG */
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
max_ch_per_tsg = g->ops.runlist.get_max_channels_per_tsg();