gpu: nvgpu: gp106: Generate new gp106 headers

Hardware headers have been outdated. Regenerate with newest tool.
At the same time correct the incorrect usage of fuse fields.

JIRA DNVGPU-172

Change-Id: If190bf0cf2e41d525e6ea374a30efd1f63963e5e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294267
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/clk/clk_vin.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -43,7 +43,7 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g,
 
 static u32 read_vin_cal_fuse_rev(struct gk20a *g)
 {
-	return fuse_vin_cal_fuse_rev_v(
+	return fuse_vin_cal_fuse_rev_data_v(
 		gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
 }
 
@@ -103,9 +103,11 @@ static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
 	if (data == 0xFFFFFFFF)
 		return -EINVAL;
 
-	gpc0interceptdata = fuse_vin_cal_gpc0_icpt_data_v(gpc0data) * 1000;
-	gpc0interceptdata = gpc0interceptdata >>
-		fuse_vin_cal_gpc0_icpt_frac_size_v();
+	gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) <<
+			     fuse_vin_cal_gpc0_icpt_frac_data_s()) +
+			    fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data);
+	gpc0interceptdata = (gpc0interceptdata * 1000U) >>
+			    fuse_vin_cal_gpc0_icpt_frac_data_s();
 
 	switch (vin_id) {
 	case CTRL_CLK_VIN_ID_GPC0:
@@ -119,33 +121,36 @@ static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
 	case CTRL_CLK_VIN_ID_SYS:
 	case CTRL_CLK_VIN_ID_XBAR:
 	case CTRL_CLK_VIN_ID_LTC:
-		interceptdata =
-			(fuse_vin_cal_gpc1_icpt_data_v(data)) * 1000;
-		interceptdata = interceptdata >>
-			fuse_vin_cal_gpc1_icpt_frac_size_v();
+		interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) <<
+				 fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) +
+				fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data);
+		interceptdata = (interceptdata * 1000U) >>
+				fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
 		break;
 
 	case CTRL_CLK_VIN_ID_SRAM:
-		interceptdata =
-			(fuse_vin_cal_sram_icpt_data_v(data)) * 1000;
-		interceptdata = interceptdata >>
-			fuse_vin_cal_sram_icpt_frac_size_v();
+		interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) <<
+				 fuse_vin_cal_sram_delta_icpt_frac_data_s()) +
+				fuse_vin_cal_sram_delta_icpt_frac_data_v(data);
+		interceptdata = (interceptdata * 1000U) >>
+				fuse_vin_cal_sram_delta_icpt_frac_data_s();
 		break;
 
 	default:
 		return -EINVAL;
 	}
 
-	if (data & fuse_vin_cal_gpc1_icpt_sign_f())
+	if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data))
 		*intercept = gpc0interceptdata - interceptdata;
 	else
 		*intercept = gpc0interceptdata + interceptdata;
 
 	/* slope */
-	gpc0slopedata = (fuse_vin_cal_gpc0_slope_data_v(gpc0data)) * 1000;
-	gpc0slopedata = gpc0slopedata >>
-		fuse_vin_cal_gpc0_slope_frac_size_v();
-
+	gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) <<
+			     fuse_vin_cal_gpc0_slope_frac_data_s()) +
+			    fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data);
+	gpc0slopedata = (gpc0slopedata * 1000U) >>
+			    fuse_vin_cal_gpc0_slope_frac_data_s();
 	switch (vin_id) {
 	case CTRL_CLK_VIN_ID_GPC0:
 		break;
@@ -160,16 +165,14 @@ static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
 	case CTRL_CLK_VIN_ID_LTC:
 	case CTRL_CLK_VIN_ID_SRAM:
 		slopedata =
-			(fuse_vin_cal_gpc1_slope_data_v(data)) * 1000;
-		slopedata = slopedata >>
-			fuse_vin_cal_gpc1_slope_frac_size_v();
+			(fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000;
 		break;
 
 	default:
 		return -EINVAL;
 	}
 
-	if (data & fuse_vin_cal_gpc1_slope_sign_f())
+	if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data))
 		*slope = gpc0slopedata - slopedata;
 	else
 		*slope = gpc0slopedata + slopedata;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -50,6 +50,30 @@
 #ifndef _hw_bus_gp106_h_
 #define _hw_bus_gp106_h_
 
+static inline u32 bus_bar0_window_r(void)
+{
+	return 0x00001700;
+}
+static inline u32 bus_bar0_window_base_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 bus_bar0_window_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
+{
+	return 0x3000000;
+}
+static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
+{
+	return 0x00000010;
+}
 static inline u32 bus_bar1_block_r(void)
 {
 	return 0x00001704;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -504,95 +504,75 @@ static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
 }
 static inline u32 fb_fbpa_fbio_delay_r(void)
 {
-	return 0x9a065c;
-}
-static inline u32 fb_fbpa_fbio_delay_src_m(void)
-{
-	return 0x7;
-}
-static inline u32 fb_fbpa_fbio_delay_src_v(u32 r)
-{
-	return (r >> 0) & 0x7;
+	return 0x009a065c;
 }
 static inline u32 fb_fbpa_fbio_delay_src_f(u32 v)
 {
-	return (v & 0x7) << 0;
+	return (v & 0xf) << 0;
+}
+static inline u32 fb_fbpa_fbio_delay_src_m(void)
+{
+	return 0xf << 0;
+}
+static inline u32 fb_fbpa_fbio_delay_src_v(u32 r)
+{
+	return (r >> 0) & 0xf;
 }
 static inline u32 fb_fbpa_fbio_delay_src_max_v(void)
 {
-	return 2;
-}
-static inline u32 fb_fbpa_fbio_delay_priv_m(void)
-{
-	return 0x7 << 4;
-}
-static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r)
-{
-	return (r >> 4) & 0x7;
+	return 0x00000002;
 }
 static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v)
 {
-	return (v & 0x7) << 4;
+	return (v & 0xf) << 4;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_m(void)
+{
+	return 0xf << 4;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r)
+{
+	return (r >> 4) & 0xf;
 }
 static inline u32 fb_fbpa_fbio_delay_priv_max_v(void)
 {
-	return 2;
+	return 0x00000002;
 }
 static inline u32 fb_fbpa_fbio_cmd_delay_r(void)
 {
-	return 0x9a08e0;
-}
-static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void)
-{
-	return 0x7;
-}
-static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r)
-{
-	return (r >> 0) & 0x7;
+	return 0x009a08e0;
 }
 static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v)
 {
-	return (v & 0x7) << 0;
+	return (v & 0xf) << 0;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void)
+{
+	return 0xf << 0;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r)
+{
+	return (r >> 0) & 0xf;
 }
 static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void)
 {
-	return 1;
-}
-static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void)
-{
-	return 0x7 << 4;
-}
-static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r)
-{
-	return (r >> 4) & 0x7;
+	return 0x00000001;
 }
 static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v)
 {
-	return (v & 0x7) << 4;
+	return (v & 0xf) << 4;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void)
+{
+	return 0xf << 4;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r)
+{
+	return (r >> 4) & 0xf;
 }
 static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void)
 {
-	return 1;
-}
-static inline u32 fb_niso_scrubber_status_r(void)
-{
-	return 0x00100b20;
-}
-static inline u32 fb_niso_scrubber_status_flag_s(void)
-{
-	return 1;
-}
-static inline u32 fb_niso_scrubber_status_flag_f(u32 v)
-{
-	return (v & 0x1) << 0;
-}
-static inline u32 fb_niso_scrubber_status_flag_m(void)
-{
-	return 0x1 << 0;
-}
-static inline u32 fb_niso_scrubber_status_flag_v(u32 r)
-{
-	return (r >> 0) & 0x1;
+	return 0x00000001;
 }
 static inline u32 fb_niso_scrub_status_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -326,6 +326,10 @@ static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
 {
 	return (v & 0x1) << (0 + i*1);
 }
+static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
+{
+	return (r >> (0 + i*1)) & 0x1;
+}
 static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
 {
 	return 0x00000004;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -124,64 +124,104 @@ static inline u32 fuse_status_opt_fbp_r(void)
 }
 static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
 {
-	return (r >> (0 + i*0)) & 0x1;
+	return (r >> (0 + i*1)) & 0x1;
 }
 static inline u32 fuse_vin_cal_fuse_rev_r(void)
 {
 	return 0x0002164c;
 }
-static inline u32 fuse_vin_cal_fuse_rev_v(u32 r)
+static inline u32 fuse_vin_cal_fuse_rev_data_v(u32 r)
 {
-	return 0x3 & r;
+	return (r >> 0) & 0x3;
 }
 static inline u32 fuse_vin_cal_gpc0_r(void)
 {
 	return 0x00021650;
 }
-static inline u32 fuse_vin_cal_gpc0_icpt_data_v(u32 r)
+static inline u32 fuse_vin_cal_gpc0_icpt_int_data_s(void)
 {
-	return ((r & 0xFFFC000) >> 14);
+	return 12;
 }
-static inline u32 fuse_vin_cal_gpc0_icpt_frac_size_v(void)
+static inline u32 fuse_vin_cal_gpc0_icpt_int_data_v(u32 r)
+{
+	return (r >> 16) & 0xfff;
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_s(void)
 {
 	return 2;
 }
-static inline u32 fuse_vin_cal_gpc0_slope_data_v(u32 r)
+static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_v(u32 r)
 {
-	return (r & 0x3FFF);
+	return (r >> 14) & 0x3;
 }
-static inline u32 fuse_vin_cal_gpc0_slope_frac_size_v(void)
+static inline u32 fuse_vin_cal_gpc0_slope_int_data_s(void)
+{
+	return 4;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_int_data_v(u32 r)
+{
+	return (r >> 10) & 0xf;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_frac_data_s(void)
 {
 	return 10;
 }
+static inline u32 fuse_vin_cal_gpc0_slope_frac_data_v(u32 r)
+{
+	return (r >> 0) & 0x3ff;
+}
 static inline u32 fuse_vin_cal_gpc1_delta_r(void)
 {
 	return 0x00021654;
 }
-static inline u32 fuse_vin_cal_gpc1_icpt_sign_f(void)
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_s(void)
 {
-	return 0x400000;
+	return 8;
 }
-static inline u32 fuse_vin_cal_gpc1_slope_sign_f(void)
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_v(u32 r)
 {
-	return 0x800;
+	return (r >> 14) & 0xff;
 }
-static inline u32 fuse_vin_cal_gpc1_icpt_data_v(u32 r)
-{
-	return ((r & 0x3FF000) >> 12);
-}
-static inline u32 fuse_vin_cal_gpc1_icpt_frac_size_v(void)
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_s(void)
 {
 	return 2;
 }
-static inline u32 fuse_vin_cal_gpc1_slope_data_v(u32 r)
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(u32 r)
 {
-	return (r & 0x7FF);
+	return (r >> 12) & 0x3;
 }
-static inline u32 fuse_vin_cal_gpc1_slope_frac_size_v(void)
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_s(void)
+{
+	return 1;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_v(u32 r)
+{
+	return (r >> 22) & 0x1;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_s(void)
+{
+	return 1;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_v(u32 r)
+{
+	return (r >> 10) & 0x1;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_s(void)
 {
 	return 10;
 }
+static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_v(u32 r)
+{
+	return (r >> 0) & 0x3ff;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_s(void)
+{
+	return 1;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_v(u32 r)
+{
+	return (r >> 11) & 0x1;
+}
 static inline u32 fuse_vin_cal_gpc2_delta_r(void)
 {
 	return 0x00021658;
@@ -206,12 +246,20 @@ static inline u32 fuse_vin_cal_sram_delta_r(void)
 {
 	return 0x0002166c;
 }
-static inline u32 fuse_vin_cal_sram_icpt_data_v(u32 r)
+static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_s(void)
 {
-	return ((r & 0x3FF000) >> 12);
+	return 9;
 }
-static inline u32 fuse_vin_cal_sram_icpt_frac_size_v(void)
+static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_v(u32 r)
+{
+	return (r >> 13) & 0x1ff;
+}
+static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_s(void)
 {
 	return 1;
 }
+static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_v(u32 r)
+{
+	return (r >> 12) & 0x1;
+}
 #endif

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void)
 {
 	return 0;
 }
+static inline u32 gmmu_new_pte_address_vid_f(u32 v)
+{
+	return (v & 0xffffff) << 8;
+}
+static inline u32 gmmu_new_pte_address_vid_w(void)
+{
+	return 0;
+}
 static inline u32 gmmu_new_pte_vol_w(void)
 {
 	return 0;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -2090,10 +2090,22 @@ static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
 {
 	return 0x00405b60 + i*4;
 }
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
+{
+	return 4;
+}
 static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
 {
 	return (v & 0xf) << 0;
 }
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
+{
+	return 4;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
+{
+	return (v & 0xf) << 4;
+}
 static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
 {
 	return (v & 0xf) << 8;
@@ -2102,6 +2114,10 @@ static inline u32 gr_cwd_sm_id_r(u32 i)
 {
 	return 0x00405ba0 + i*4;
 }
+static inline u32 gr_cwd_sm_id__size_1_v(void)
+{
+	return 0x00000010;
+}
 static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
 {
 	return (v & 0xff) << 0;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pram_gp106_h_
+#define _hw_pram_gp106_h_
+
+static inline u32 pram_data032_r(u32 i)
+{
+	return 0x00700000 + i*4;
+}
+#endif

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -154,6 +154,14 @@ static inline u32 top_device_info_type_enum_copy0_f(void)
 {
 	return 0x4;
 }
+static inline u32 top_device_info_type_enum_copy2_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 top_device_info_type_enum_copy2_f(void)
+{
+	return 0xc;
+}
 static inline u32 top_device_info_type_enum_lce_v(void)
 {
 	return 0x00000013;
@@ -162,6 +170,22 @@ static inline u32 top_device_info_type_enum_lce_f(void)
 {
 	return 0x4c;
 }
+static inline u32 top_device_info_engine_v(u32 r)
+{
+	return (r >> 5) & 0x1;
+}
+static inline u32 top_device_info_runlist_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 top_device_info_intr_v(u32 r)
+{
+	return (r >> 3) & 0x1;
+}
+static inline u32 top_device_info_reset_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
 static inline u32 top_device_info_entry_v(u32 r)
 {
 	return (r >> 0) & 0x3;
@@ -174,6 +198,10 @@ static inline u32 top_device_info_entry_enum_v(void)
 {
 	return 0x00000002;
 }
+static inline u32 top_device_info_entry_engine_type_v(void)
+{
+	return 0x00000003;
+}
 static inline u32 top_device_info_entry_data_v(void)
 {
 	return 0x00000001;