nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Add checking for non safety code

Browse Source 
Add checking for unused non safety code in the
gr interrupt unit.
Add #ifdef CONFIG_NVGPU_HAL_NON_FUSA checking for
gm20b_gr_intr_tpc_exception_sm_enable function which is not being
called in safety code.
Add #ifdef CONFIG_NVGPU_DEBUGGER checking for
gm20b_gr_intr_tpc_exception_sm_disable function which is needed
with debugger enable.

Jira NVGPU-4085

Change-Id: Ie721505cdfced5b6b0443624d6e7cca2a0d4a19a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208918
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-09-30 14:02:28 -07:00
committed by Alex Waterman
parent 425f0871d2
commit c0684633d2
9 changed files with 54 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
View File

@@ -346,6 +346,19 @@ u32 gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g)
return global_esr_mask;
}
void gm20b_gr_intr_tpc_exception_sm_enable(struct gk20a *g)
{
u32 tpc_exception_en = nvgpu_readl(g,
gr_gpc0_tpc0_tpccs_tpc_exception_en_r());
tpc_exception_en &=
~gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f();
tpc_exception_en |= gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f();
nvgpu_writel(g,
gr_gpcs_tpcs_tpccs_tpc_exception_en_r(),
tpc_exception_en);
}
#ifdef CONFIG_NVGPU_DEBUGGER
u64 gm20b_gr_intr_tpc_enabled_exceptions(struct gk20a *g)
{

4
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.h
View File

@@ -55,9 +55,8 @@ u32 gm20b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
struct nvgpu_gr_tpc_exception *pending_tpc);
void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable);
u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g);
void gm20ab_gr_intr_tpc_exception_sm_disable(struct gk20a *g, u32 offset);
void gm20ab_gr_intr_tpc_exception_sm_enable(struct gk20a *g);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gm20b_gr_intr_tpc_exception_sm_enable(struct gk20a *g);
int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data);
void gm20b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
@@ -83,6 +82,7 @@ u32 gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
#ifdef CONFIG_NVGPU_DEBUGGER
u64 gm20b_gr_intr_tpc_enabled_exceptions(struct gk20a *g);
void gm20b_gr_intr_tpc_exception_sm_disable(struct gk20a *g, u32 offset);
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif /* NVGPU_GR_INTR_GM20B_H */

41
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c
View File

@@ -408,32 +408,6 @@ void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable)
}
void gm20ab_gr_intr_tpc_exception_sm_disable(struct gk20a *g, u32 offset)
{
u32 tpc_exception_en = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_tpccs_tpc_exception_en_r(),
offset));
tpc_exception_en &=
~gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f();
nvgpu_writel(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_tpccs_tpc_exception_en_r(), offset),
tpc_exception_en);
}
void gm20ab_gr_intr_tpc_exception_sm_enable(struct gk20a *g)
{
u32 tpc_exception_en = nvgpu_readl(g,
gr_gpc0_tpc0_tpccs_tpc_exception_en_r());
tpc_exception_en &=
~gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f();
tpc_exception_en |= gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f();
nvgpu_writel(g,
gr_gpcs_tpcs_tpccs_tpc_exception_en_r(),
tpc_exception_en);
}
u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g)
{
u32 ops = 0;
@@ -450,3 +424,18 @@ u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g)
}
return ops;
}
#ifdef CONFIG_NVGPU_DEBUGGER
void gm20b_gr_intr_tpc_exception_sm_disable(struct gk20a *g, u32 offset)
{
u32 tpc_exception_en = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_tpccs_tpc_exception_en_r(),
offset));
tpc_exception_en &=
~gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f();
nvgpu_writel(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_tpccs_tpc_exception_en_r(), offset),
tpc_exception_en);
}
#endif

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.h
View File

@@ -43,8 +43,10 @@ struct nvgpu_gr_isr_data;
int gp10b_gr_intr_handle_fecs_error(struct gk20a *g,
struct nvgpu_channel *ch_ptr,
struct nvgpu_gr_isr_data *isr_data);
#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
void gp10b_gr_intr_set_coalesce_buffer_size(struct gk20a *g, u32 data);
void gp10b_gr_intr_set_go_idle_timeout(struct gk20a *g, u32 data);
#endif
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gp10b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc);
int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b_fusa.c
View File

@@ -182,6 +182,7 @@ clean_up:
return nvgpu_gr_intr_handle_fecs_error(g, ch_ptr, isr_data);
}
#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
void gp10b_gr_intr_set_go_idle_timeout(struct gk20a *g, u32 data)
{
nvgpu_writel(g, gr_fe_go_idle_timeout_r(), data);
@@ -200,3 +201,4 @@ void gp10b_gr_intr_set_coalesce_buffer_size(struct gk20a *g, u32 data)
nvgpu_log_fn(g, "done");
}
#endif

6
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -475,9 +475,7 @@ static const struct gpu_ops gm20b_ops = {
.enable_exceptions = gm20b_gr_intr_enable_exceptions,
.nonstall_isr = gm20b_gr_intr_nonstall_isr,
.tpc_exception_sm_enable =
gm20ab_gr_intr_tpc_exception_sm_enable,
.tpc_exception_sm_disable =
gm20ab_gr_intr_tpc_exception_sm_disable,
gm20b_gr_intr_tpc_exception_sm_enable,
.handle_sm_exception =
nvgpu_gr_intr_handle_sm_exception,
.stall_isr = nvgpu_gr_intr_stall_isr,
@@ -495,6 +493,8 @@ static const struct gpu_ops gm20b_ops = {
.get_sm_no_lock_down_hww_global_esr_mask =
gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_exception_sm_disable =
gm20b_gr_intr_tpc_exception_sm_disable,
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif

6
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -555,9 +555,7 @@ static const struct gpu_ops gp10b_ops = {
.enable_exceptions = gm20b_gr_intr_enable_exceptions,
.nonstall_isr = gm20b_gr_intr_nonstall_isr,
.tpc_exception_sm_enable =
gm20ab_gr_intr_tpc_exception_sm_enable,
.tpc_exception_sm_disable =
gm20ab_gr_intr_tpc_exception_sm_disable,
gm20b_gr_intr_tpc_exception_sm_enable,
.handle_sm_exception =
gp10b_gr_intr_handle_sm_exception,
.stall_isr = nvgpu_gr_intr_stall_isr,
@@ -575,6 +573,8 @@ static const struct gpu_ops gp10b_ops = {
.get_sm_no_lock_down_hww_global_esr_mask =
gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_exception_sm_disable =
gm20b_gr_intr_tpc_exception_sm_disable,
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif

14
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -673,10 +673,6 @@ static const struct gpu_ops gv11b_ops = {
gv11b_gr_intr_enable_gpc_exceptions,
.enable_exceptions = gv11b_gr_intr_enable_exceptions,
.nonstall_isr = gm20b_gr_intr_nonstall_isr,
.tpc_exception_sm_enable =
gm20ab_gr_intr_tpc_exception_sm_enable,
.tpc_exception_sm_disable =
gm20ab_gr_intr_tpc_exception_sm_disable,
.handle_sm_exception =
nvgpu_gr_intr_handle_sm_exception,
.stall_isr = nvgpu_gr_intr_stall_isr,
@@ -698,12 +694,18 @@ static const struct gpu_ops gv11b_ops = {
gv11b_gr_intr_get_sm_hww_global_esr,
.get_sm_no_lock_down_hww_global_esr_mask =
gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
.get_ctxsw_checksum_mismatch_mailbox_val =
gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.tpc_exception_sm_enable =
gm20b_gr_intr_tpc_exception_sm_enable,
#endif
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_exception_sm_disable =
gm20b_gr_intr_tpc_exception_sm_disable,
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif
.get_ctxsw_checksum_mismatch_mailbox_val =
gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
},
.falcon = {
.handle_fecs_ecc_error =

10
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -694,10 +694,6 @@ static const struct gpu_ops tu104_ops = {
.enable_gpc_exceptions =
tu104_gr_intr_enable_gpc_exceptions,
.enable_exceptions = gv11b_gr_intr_enable_exceptions,
.tpc_exception_sm_enable =
gm20ab_gr_intr_tpc_exception_sm_enable,
.tpc_exception_sm_disable =
gm20ab_gr_intr_tpc_exception_sm_disable,
.handle_sm_exception =
nvgpu_gr_intr_handle_sm_exception,
.stall_isr = nvgpu_gr_intr_stall_isr,
@@ -720,7 +716,13 @@ static const struct gpu_ops tu104_ops = {
gv11b_gr_intr_get_sm_hww_global_esr,
.get_sm_no_lock_down_hww_global_esr_mask =
gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.tpc_exception_sm_enable =
gm20b_gr_intr_tpc_exception_sm_enable,
#endif
#ifdef CONFIG_NVGPU_DEBUGGER
.tpc_exception_sm_disable =
gm20b_gr_intr_tpc_exception_sm_disable,
.tpc_enabled_exceptions =
gm20b_gr_intr_tpc_enabled_exceptions,
#endif