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gpu: nvgpu: add chip specific sync point support

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Added support for chip specific sync point implementation.
Relevant fifo hal functions are added and updated for
legacy chips.

JIRA GPUT19X-2

Change-Id: I9a9c36d71e15c384b5e5af460cd52012f94e0b04
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1258232
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2017-03-17 11:30:57 -07:00
committed by mobile promotions
parent e21e6e947b
commit c0822cb22e
6 changed files with 166 additions and 55 deletions
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83
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -4265,6 +4265,79 @@ u32 gk20a_fifo_pbdma_acquire_val(u64 timeout)
return val;
}
#ifdef CONFIG_TEGRA_GK20A_NVHOST
void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va)
{
gk20a_dbg_fn("");
off = cmd->off + off;
/* syncpoint_a */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001C);
/* payload */
nvgpu_mem_wr32(g, cmd->mem, off++, thresh);
/* syncpoint_b */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001D);
/* syncpt_id, switch_en, wait */
nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x10);
}
u32 gk20a_fifo_get_syncpt_wait_cmd_size(void)
{
return 4;
}
void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g,
bool wfi_cmd, struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va)
{
u32 off = cmd->off;
gk20a_dbg_fn("");
if (wfi_cmd) {
/* wfi */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001E);
/* handle, ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x00000000);
}
/* syncpoint_a */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001C);
/* payload, ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0);
/* syncpoint_b */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001D);
/* syncpt_id, incr */
nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x1);
/* syncpoint_b */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001D);
/* syncpt_id, incr */
nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x1);
}
u32 gk20a_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd)
{
if (wfi_cmd)
return 8;
else
return 6;
}
void gk20a_fifo_free_syncpt_buf(struct channel_gk20a *c,
struct nvgpu_mem *syncpt_buf)
{
}
int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
{
return 0;
}
#endif
void gk20a_init_fifo(struct gpu_ops *gops)
{
gops->fifo.disable_channel = gk20a_fifo_disable_channel;
@@ -4312,4 +4385,14 @@ void gk20a_init_fifo(struct gpu_ops *gops)
gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0;
#ifdef CONFIG_TEGRA_GK20A_NVHOST
gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf;
gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf;
gops->fifo.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd;
gops->fifo.get_syncpt_wait_cmd_size =
gk20a_fifo_get_syncpt_wait_cmd_size;
gops->fifo.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd;
gops->fifo.get_syncpt_incr_cmd_size =
gk20a_fifo_get_syncpt_incr_cmd_size;
#endif
}