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gpu: nvgpu: remove hw_top_gv100.h include from gr_gv100.c

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In gr_gv100_get_active_fpba_mask(), we directly access top_* register
from hw_top_gv100.h h/w header to read FBPA count.

Add a new HAL in TOP unit to return max FBPA count
g->ops.top.get_max_fbpas_count()

Use this HAL in gr_gv100.c to get FBPA count and remove direct access
of top_* register, and also remove hw_top_gv100.h header include

Jira NVGPU-2895

Change-Id: Idfba553b24d7d6abf124a84b1490987e8cbf1985
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069470
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-03-04 15:45:32 +05:30
committed by mobile promotions
parent 300f734f9f
commit c0a0b6419d
6 changed files with 16 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/common/top/top_gv100.c
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@@ -64,3 +64,11 @@ void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val)
top_nvhsclk_ctrl_swap_clk_nvl_f(val));
nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg);
}
u32 gv100_top_get_max_fbpas_count(struct gk20a *g)
{
u32 tmp;
tmp = nvgpu_readl(g, top_num_fbpas_r());
return top_num_fbpas_value_v(tmp);
}

2
drivers/gpu/nvgpu/common/top/top_gv100.h
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@@ -34,4 +34,6 @@ void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val);
u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g);
void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val);
u32 gv100_top_get_max_fbpas_count(struct gk20a *g);
#endif

6
drivers/gpu/nvgpu/gv100/gr_gv100.c
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@@ -38,7 +38,6 @@
#include <nvgpu/hw/gv100/hw_gr_gv100.h>
#include <nvgpu/hw/gv100/hw_proj_gv100.h>
#include <nvgpu/hw/gv100/hw_top_gv100.h>
#include <nvgpu/hw/gv100/hw_perf_gv100.h>
@@ -365,10 +364,9 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g)
static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g)
{
u32 active_fbpa_mask;
u32 num_fbpas, val;
u32 num_fbpas;
val = nvgpu_readl(g, top_num_fbpas_r());
num_fbpas = top_num_fbpas_value_v(val);
num_fbpas = g->ops.top.get_max_fbpas_count(g);
/*
* Read active fbpa mask from fuse

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
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@@ -1163,6 +1163,7 @@ static const struct gpu_ops gv100_ops = {
.get_max_tpc_per_gpc_count =
gm20b_top_get_max_tpc_per_gpc_count,
.get_max_fbps_count = gm20b_top_get_max_fbps_count,
.get_max_fbpas_count = gv100_top_get_max_fbpas_count,
.get_max_ltc_per_fbp = gm20b_top_get_max_ltc_per_fbp,
.get_max_lts_per_ltc = gm20b_top_get_max_lts_per_ltc,
},

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
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@@ -1619,6 +1619,7 @@ struct gpu_ops {
u32 (*get_max_gpc_count)(struct gk20a *g);
u32 (*get_max_tpc_per_gpc_count)(struct gk20a *g);
u32 (*get_max_fbps_count)(struct gk20a *g);
u32 (*get_max_fbpas_count)(struct gk20a *g);
u32 (*get_max_ltc_per_fbp)(struct gk20a *g);
u32 (*get_max_lts_per_ltc)(struct gk20a *g);
} top;

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -76,6 +76,7 @@
#include "common/nvdec/nvdec_tu104.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/top/top_gv100.h"
#include "common/nvlink/init/device_reginit_gv100.h"
#include "common/nvlink/intr_and_err_handling_gv100.h"
#include "hal/nvlink/minion_gv100.h"
@@ -1209,6 +1210,7 @@ static const struct gpu_ops tu104_ops = {
.get_max_tpc_per_gpc_count =
gm20b_top_get_max_tpc_per_gpc_count,
.get_max_fbps_count = gm20b_top_get_max_fbps_count,
.get_max_fbpas_count = gv100_top_get_max_fbpas_count,
.get_max_ltc_per_fbp = gm20b_top_get_max_ltc_per_fbp,
.get_max_lts_per_ltc = gm20b_top_get_max_lts_per_ltc,
},