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gpu: nvgpu: Use sw ops for Perfmon

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Some functions are not accessing hardware directly
but are being called using HAL ops: For example

.pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
.pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,

These were being called by:
g->ops.pmu.pmu_init_perfmon,
g->ops.pmu.pmu_perfmon_start_sampling,
g->ops.pmu.pmu_perfmon_stop_sampling,
g->ops.pmu.pmu_perfmon_get_samples_rpc

Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_perfmon_init(struct gk20a *g,
	struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_start_sampling_perfmon(struct gk20a *g,
	struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_stop_sampling_perfmon(struct gk20a *g,
	struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_get_samples_rpc_perfmon(struct gk20a *g,
	struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);

and based on hardware chip call the chip specific
perfmon sw init function: nvgpu_gv11b_perfmon_sw_init() and
nvgpu_gv100_perfmon_sw_init() and assign the sw ops for perfmon

JIRA NVGPU-3210

Change-Id: I2470863f87a7969e3c0454fa48761499b08d445c
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109899
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2019-04-30 15:29:50 +05:30
committed by mobile promotions
parent 1cd29cc075
commit c19d7e3911
19 changed files with 241 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile
View File

@@ -75,6 +75,8 @@ nvgpu-y += \
common/pmu/pg/pmu_pg.o \
common/pmu/pg/pmu_aelpg.o \
common/pmu/perfmon/pmu_perfmon.o \
common/pmu/perfmon/pmu_perfmon_sw_gm20b.o \
common/pmu/perfmon/pmu_perfmon_sw_gv11b.o \
common/pmu/pmu_debug.o \
common/pmu/pg/pg_sw_gm20b.o \
common/pmu/pg/pg_sw_gp10b.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -131,6 +131,8 @@ srcs += common/sim/sim.c \
common/pmu/pg/pmu_pg.c \
common/pmu/pg/pmu_aelpg.c \
common/pmu/perfmon/pmu_perfmon.c \
common/pmu/perfmon/pmu_perfmon_sw_gm20b.c \
common/pmu/perfmon/pmu_perfmon_sw_gv11b.c \
common/pmu/pmu_debug.c \
common/pmu/pg/pg_sw_gm20b.c \
common/pmu/pg/pg_sw_gp10b.c \

3
drivers/gpu/nvgpu/common/pmu/ipc/pmu_msg.c
View File

@@ -507,7 +507,8 @@ int nvgpu_pmu_process_message(struct nvgpu_pmu *pmu)
nvgpu_pmu_lsfm_int_wpr_region(g, pmu, pmu->lsfm);
if (nvgpu_is_enabled(g, NVGPU_PMU_PERFMON)) {
g->ops.pmu.pmu_init_perfmon(pmu);
nvgpu_pmu_perfmon_initialization(g, pmu,
pmu->pmu_perfmon);
}
return 0;

94
drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c
View File

@@ -32,6 +32,9 @@
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/kmem.h>
#include "pmu_perfmon_sw_gm20b.h"
#include "pmu_perfmon_sw_gv11b.h"
static u8 get_perfmon_id(struct nvgpu_pmu *pmu)
{
struct gk20a *g = pmu->g;
@@ -93,25 +96,55 @@ void nvgpu_pmu_perfmon_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
}
}
int nvgpu_pmu_initialize_perfmon(struct gk20a *g, struct nvgpu_pmu *pmu)
int nvgpu_pmu_initialize_perfmon(struct gk20a *g, struct nvgpu_pmu *pmu,
struct nvgpu_pmu_perfmon **perfmon_ptr)
{
if (pmu->pmu_perfmon != NULL) {
struct nvgpu_pmu_perfmon *perfmon;
int err = 0;
u32 ver = g->params.gpu_arch + g->params.gpu_impl;
if (*perfmon_ptr != NULL) {
/* Not to allocate a new buffer after railgating
is done. Use the same memory for pmu_perfmon
is done. Use the same memory for pmu_perfmon
after railgating.
*/
return 0;
nvgpu_pmu_dbg(g, "skip perfmon init for unrailgate sequence");
goto exit;
} else {
/* One-time memory allocation for pmu_perfmon */
pmu->pmu_perfmon = (struct nvgpu_pmu_perfmon *)(nvgpu_kzalloc(g,
sizeof(struct nvgpu_pmu_perfmon)));
if (pmu->pmu_perfmon == NULL) {
nvgpu_err(g, "failed to initialize perfmon");
return -ENOMEM;
}
}
return 0;
/* One-time memory allocation for pmu_perfmon */
perfmon = (struct nvgpu_pmu_perfmon *)
nvgpu_kzalloc(g, sizeof(struct nvgpu_pmu_perfmon));
if (perfmon == NULL) {
nvgpu_err(g, "failed to initialize perfmon");
return -ENOMEM;
}
*perfmon_ptr = perfmon;
switch (ver) {
case GK20A_GPUID_GM20B:
case GK20A_GPUID_GM20B_B:
case NVGPU_GPUID_GP10B:
case NVGPU_GPUID_GV100:
case NVGPU_GPUID_TU104:
nvgpu_gm20b_perfmon_sw_init(g, *perfmon_ptr);
break;
case NVGPU_GPUID_GV11B:
nvgpu_gv11b_perfmon_sw_init(g, *perfmon_ptr);
break;
default:
nvgpu_kfree(g, *perfmon_ptr);
err = -EINVAL;
nvgpu_err(g, "no support for GPUID %x", ver);
break;
}
exit:
return err;
}
@@ -209,6 +242,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu)
return 0;
}
int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu)
{
struct gk20a *g = pmu->g;
@@ -324,8 +358,8 @@ int nvgpu_pmu_load_update(struct gk20a *g)
return 0;
}
if (g->ops.pmu.pmu_perfmon_get_samples_rpc != NULL) {
nvgpu_pmu_perfmon_get_samples_rpc(pmu);
if (pmu->pmu_perfmon->get_samples_rpc != NULL) {
nvgpu_pmu_perfmon_get_sample(g, pmu, pmu->pmu_perfmon);
load = pmu->pmu_perfmon->load;
} else {
err = nvgpu_falcon_copy_from_dmem(&pmu->flcn,
@@ -444,7 +478,8 @@ int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu,
/* restart sampling */
if (pmu->pmu_perfmon->perfmon_sampling_enabled) {
return g->ops.pmu.pmu_perfmon_start_sampling(&(g->pmu));
return nvgpu_pmu_perfmon_start_sample(g, pmu,
pmu->pmu_perfmon);
}
return 0;
@@ -599,3 +634,30 @@ u32 nvgpu_pmu_perfmon_get_load_avg(struct nvgpu_pmu *pmu)
{
return pmu->pmu_perfmon->load_avg;
}
int nvgpu_pmu_perfmon_initialization(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon)
{
return perfmon->init_perfmon(pmu);
}
int nvgpu_pmu_perfmon_start_sample(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon)
{
return perfmon->start_sampling(pmu);
}
int nvgpu_pmu_perfmon_stop_sample(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon)
{
return perfmon->stop_sampling(pmu);
}
int nvgpu_pmu_perfmon_get_sample(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon)
{
return perfmon->get_samples_rpc(pmu);
}

39
drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_gm20b.c Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/pmu/pmu_perfmon.h>
#include "pmu_perfmon_sw_gm20b.h"
void nvgpu_gm20b_perfmon_sw_init(struct gk20a *g,
struct nvgpu_pmu_perfmon *perfmon)
{
nvgpu_log_fn(g, " ");
perfmon->init_perfmon = nvgpu_pmu_init_perfmon;
perfmon->start_sampling =
nvgpu_pmu_perfmon_start_sampling;
perfmon->stop_sampling =
nvgpu_pmu_perfmon_stop_sampling;
perfmon->get_samples_rpc = NULL;
}

29
drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_gm20b.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PMU_PERFMON_SW_GM20B_H
#define NVGPU_PMU_PERFMON_SW_GM20B_H
void nvgpu_gm20b_perfmon_sw_init(struct gk20a *g,
struct nvgpu_pmu_perfmon *perfmon);
#endif /* NVGPU_PMU_PERMON_SW_GM20B_H */

39
drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_gv11b.c Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/pmu/pmu_perfmon.h>
#include "pmu_perfmon_sw_gv11b.h"
void nvgpu_gv11b_perfmon_sw_init(struct gk20a *g,
struct nvgpu_pmu_perfmon *perfmon)
{
nvgpu_log_fn(g, " ");
perfmon->init_perfmon = nvgpu_pmu_init_perfmon_rpc;
perfmon->start_sampling =
nvgpu_pmu_perfmon_start_sampling_rpc;
perfmon->stop_sampling =
nvgpu_pmu_perfmon_stop_sampling_rpc;
perfmon->get_samples_rpc =
nvgpu_pmu_perfmon_get_samples_rpc;
}

29
drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_gv11b.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PERFMON_SW_GV11B_H
#define NVGPU_PERFMON_SW_GV11B_H
void nvgpu_gv11b_perfmon_sw_init(struct gk20a *g,
struct nvgpu_pmu_perfmon *perfmon);
#endif /* NVGPU_PERMON_SW_GV11B_H */

2
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -374,7 +374,7 @@ int nvgpu_early_init_pmu_sw(struct gk20a *g, struct nvgpu_pmu *pmu)
}
/* Allocate memory for pmu_perfmon */
err = nvgpu_pmu_initialize_perfmon(g, pmu);
err = nvgpu_pmu_initialize_perfmon(g, pmu, &pmu->pmu_perfmon);
if (err != 0) {
goto exit;
}

3
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -636,9 +636,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.pmu_enable_irq = NULL,
.write_dmatrfbase = NULL,
.pmu_elpg_statistics = NULL,
.pmu_init_perfmon = NULL,
.pmu_perfmon_start_sampling = NULL,
.pmu_perfmon_stop_sampling = NULL,
.pmu_pg_init_param = NULL,
.pmu_pg_supported_engines_list = NULL,
.pmu_pg_engines_feature_list = NULL,

4
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -724,10 +724,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.pmu_enable_irq = NULL,
.write_dmatrfbase = NULL,
.pmu_elpg_statistics = NULL,
.pmu_init_perfmon = NULL,
.pmu_perfmon_start_sampling = NULL,
.pmu_perfmon_stop_sampling = NULL,
.pmu_perfmon_get_samples_rpc = NULL,
.pmu_pg_init_param = NULL,
.pmu_pg_supported_engines_list = NULL,
.pmu_pg_engines_feature_list = NULL,

3
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -799,9 +799,6 @@ static const struct gpu_ops gm20b_ops = {
.pmu_enable_irq = gk20a_pmu_enable_irq,
.write_dmatrfbase = gm20b_write_dmatrfbase,
.pmu_elpg_statistics = gm20b_pmu_elpg_statistics,
.pmu_init_perfmon = nvgpu_pmu_init_perfmon,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling,
.pmu_pg_init_param = NULL,
.pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list,
.pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list,

3
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -874,9 +874,6 @@ static const struct gpu_ops gp10b_ops = {
.pmu_enable_irq = gk20a_pmu_enable_irq,
.write_dmatrfbase = gp10b_write_dmatrfbase,
.pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
.pmu_init_perfmon = nvgpu_pmu_init_perfmon,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling,
.pmu_pg_init_param = gp10b_pg_gr_init,
.pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list,
.pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list,

3
drivers/gpu/nvgpu/hal/init/hal_gv100.c
View File

@@ -1028,9 +1028,6 @@ static const struct gpu_ops gv100_ops = {
.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
.pmu_enable_irq = gk20a_pmu_enable_irq,
.is_pmu_supported = gp106_is_pmu_supported,
.pmu_init_perfmon = nvgpu_pmu_init_perfmon,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling,
.pmu_mutex_owner = gk20a_pmu_mutex_owner,
.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
.pmu_msgq_tail = gk20a_pmu_msgq_tail,

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1030,10 +1030,6 @@ static const struct gpu_ops gv11b_ops = {
.pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter,
.pmu_read_idle_intr_status = gk20a_pmu_read_idle_intr_status,
.pmu_clear_idle_intr_status = gk20a_pmu_clear_idle_intr_status,
.pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
.pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,
/* debug */
.dump_secure_fuses = pmu_dump_security_fuses_gm20b,
.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,

3
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1069,9 +1069,6 @@ static const struct gpu_ops tu104_ops = {
.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
.pmu_enable_irq = gk20a_pmu_enable_irq,
.is_pmu_supported = tu104_is_pmu_supported,
.pmu_init_perfmon = nvgpu_pmu_init_perfmon,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling,
.pmu_mutex_owner = gk20a_pmu_mutex_owner,
.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
.pmu_msgq_tail = gk20a_pmu_msgq_tail,

5
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1423,11 +1423,6 @@ struct gpu_ops {
* PMU RTOS FW version ops, should move under struct nvgpu_pmu's
* pg/perfmon unit struct ops
*/
/* perfmon */
int (*pmu_init_perfmon)(struct nvgpu_pmu *pmu);
int (*pmu_perfmon_start_sampling)(struct nvgpu_pmu *pmu);
int (*pmu_perfmon_stop_sampling)(struct nvgpu_pmu *pmu);
int (*pmu_perfmon_get_samples_rpc)(struct nvgpu_pmu *pmu);
/* pg */
int (*pmu_elpg_statistics)(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data);

17
drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_perfmon.h
View File

@@ -45,13 +45,18 @@ struct nvgpu_pmu_perfmon {
u32 load;
bool perfmon_ready;
bool perfmon_sampling_enabled;
int (*init_perfmon)(struct nvgpu_pmu *pmu);
int (*start_sampling)(struct nvgpu_pmu *pmu);
int (*stop_sampling)(struct nvgpu_pmu *pmu);
int (*get_samples_rpc)(struct nvgpu_pmu *pmu);
};
/* perfmon */
void nvgpu_pmu_perfmon_rpc_handler(struct gk20a *g, struct nvgpu_pmu *pmu,
struct nv_pmu_rpc_header *rpc,
struct rpc_handler_payload *rpc_payload);
int nvgpu_pmu_initialize_perfmon(struct gk20a *g, struct nvgpu_pmu *pmu);
int nvgpu_pmu_initialize_perfmon(struct gk20a *g, struct nvgpu_pmu *pmu,
struct nvgpu_pmu_perfmon **perfmon_ptr);
void nvgpu_pmu_deinitialize_perfmon(struct gk20a *g, struct nvgpu_pmu *pmu);
int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu);
int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu);
@@ -74,4 +79,14 @@ void nvgpu_pmu_perfmon_set_sampling_enable_status(struct nvgpu_pmu *pmu,
u64 nvgpu_pmu_perfmon_get_events_count(struct nvgpu_pmu *pmu);
u32 nvgpu_pmu_perfmon_get_load_avg(struct nvgpu_pmu *pmu);
/* perfmon SW Ops */
int nvgpu_pmu_perfmon_initialization(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_perfmon_start_sample(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_perfmon_stop_sample(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_perfmon_get_sample(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
#endif /* NVGPU_PMU_PERFMON_H */

6
drivers/gpu/nvgpu/os/linux/debug_pmu.c
View File

@@ -357,13 +357,15 @@ static ssize_t perfmon_events_enable_write(struct file *file,
&& nvgpu_is_enabled(g, NVGPU_PMU_PERFMON)) {
nvgpu_pmu_perfmon_set_sampling_enable_status(&(g->pmu),
true);
g->ops.pmu.pmu_perfmon_start_sampling(&(g->pmu));
nvgpu_pmu_perfmon_start_sample(g, &(g->pmu),
g->pmu.pmu_perfmon);
} else if (!val
&& nvgpu_pmu_perfmon_get_sampling_enable_status(&(g->pmu))
&& nvgpu_is_enabled(g, NVGPU_PMU_PERFMON)) {
nvgpu_pmu_perfmon_set_sampling_enable_status(&(g->pmu),
false);
g->ops.pmu.pmu_perfmon_stop_sampling(&(g->pmu));
nvgpu_pmu_perfmon_stop_sample(g, &(g->pmu),
g->pmu.pmu_perfmon);
}
gk20a_idle(g);
} else {