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gpu: nvgpu: Fix CERT-C L1 defects

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- CID 588842
- CID 588848

Bug 3512545

Change-Id: Icc804715c086ce6abc1df37ed6be9ea578d01623
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2836068
Reviewed-by: Vivek Kumar (SW-TEGRA) <vivekku@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
srajum
2023-01-02 17:27:18 +05:30
committed by mobile promotions
parent 3e2eff564f
commit c1a1a14086
1 changed files with 7 additions and 3 deletions
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6
drivers/gpu/nvgpu/common/nvs/nvs_sched_ctrl.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -576,11 +576,15 @@ void nvgpu_nvs_buffer_free(struct nvgpu_nvs_domain_ctrl_fifo *sched_ctrl,
if (mask == NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_WRITE) { if (mask == NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_WRITE) {
nvgpu_nvs_domain_ctrl_fifo_set_receiver(g, NULL); nvgpu_nvs_domain_ctrl_fifo_set_receiver(g, NULL);
if (send_queue_receiver != NULL) {
nvs_control_fifo_receiver_exit(g, send_queue_receiver); nvs_control_fifo_receiver_exit(g, send_queue_receiver);
}
} else if (mask == NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_READ) { } else if (mask == NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_READ) {
nvgpu_nvs_domain_ctrl_fifo_set_sender(g, NULL); nvgpu_nvs_domain_ctrl_fifo_set_sender(g, NULL);
if (receiver_queue_sender != NULL) {
nvs_control_fifo_sender_exit(g, receiver_queue_sender); nvs_control_fifo_sender_exit(g, receiver_queue_sender);
} }
}
#endif #endif
if (nvgpu_mem_is_valid(&buf->mem)) { if (nvgpu_mem_is_valid(&buf->mem)) {