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gpu: nvgpu: Fix CERT-C L1 defects
- CID 588842 - CID 588848 Bug 3512545 Change-Id: Icc804715c086ce6abc1df37ed6be9ea578d01623 Signed-off-by: srajum <srajum@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2836068 Reviewed-by: Vivek Kumar (SW-TEGRA) <vivekku@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -576,11 +576,15 @@ void nvgpu_nvs_buffer_free(struct nvgpu_nvs_domain_ctrl_fifo *sched_ctrl,
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if (mask == NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_WRITE) {
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nvgpu_nvs_domain_ctrl_fifo_set_receiver(g, NULL);
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if (send_queue_receiver != NULL) {
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nvs_control_fifo_receiver_exit(g, send_queue_receiver);
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}
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} else if (mask == NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_READ) {
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nvgpu_nvs_domain_ctrl_fifo_set_sender(g, NULL);
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if (receiver_queue_sender != NULL) {
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nvs_control_fifo_sender_exit(g, receiver_queue_sender);
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}
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}
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#endif
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if (nvgpu_mem_is_valid(&buf->mem)) {
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