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gpu: nvgpu: remove clk_common.c

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clk/clk_common.c includes some linux specific clock
calls which can be easily replaced

Move linux specific call to platform file
Rest of the APIs are removed by directly substituting
API code into caller function

Jira NVGPU-49

Change-Id: Ia70e7a65c877649699b5d064683c34c0cb696d2e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483862
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2017-05-22 12:19:38 +05:30
committed by mobile promotions
parent ec964208c1
commit c32aa0170d
5 changed files with 34 additions and 77 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile.nvgpu
View File

@@ -139,7 +139,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
nvgpu-$(CONFIG_COMMON_CLK) += \
tegra/linux/clk.o \
clk/clk_common.o \
gm20b/clk_gm20b.o
nvgpu-$(CONFIG_GK20A_DEVFREQ) += \

62
drivers/gpu/nvgpu/clk/clk_common.c
View File

@@ -1,62 +0,0 @@
/*
* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include "gk20a/gk20a.h"
#include "gk20a/platform_gk20a.h"
struct clk *gk20a_clk_get(struct gk20a *g)
{
if (!g->clk.tegra_clk) {
struct clk *clk;
char clk_dev_id[32];
struct device *dev = dev_from_gk20a(g);
snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev));
clk = clk_get_sys(clk_dev_id, "gpu");
if (IS_ERR(clk)) {
nvgpu_err(g, "fail to get tegra gpu clk %s/gpu\n",
clk_dev_id);
return NULL;
}
g->clk.tegra_clk = clk;
}
return g->clk.tegra_clk;
}
unsigned long gk20a_clk_get_rate(struct gk20a *g)
{
struct clk_gk20a *clk = &g->clk;
return rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
}
long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate)
{
/* make sure the clock is available */
if (!gk20a_clk_get(g))
return rate;
return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate);
}
int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate)
{
return clk_set_rate(g->clk.tegra_clk, rate);
}

6
drivers/gpu/nvgpu/gk20a/clk_gk20a.h
View File

@@ -105,12 +105,6 @@ struct clk_gk20a {
struct gpu_ops;
/* APIs used for both GK20A and GM20B */
unsigned long gk20a_clk_get_rate(struct gk20a *g);
int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate);
long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate);
struct clk *gk20a_clk_get(struct gk20a *g);
#define KHZ 1000
#define MHZ 1000000

11
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
View File

@@ -1147,11 +1147,6 @@ int gm20b_init_clk_setup_sw(struct gk20a *g)
clk->pll_poweron_uv = BOOT_GPU_UV_B1;
}
if (!gk20a_clk_get(g)) {
err = -EINVAL;
goto fail;
}
clk->gpc_pll.clk_in = g->ops.clk.get_ref_clock_rate(g) / KHZ;
if (clk->gpc_pll.clk_in == 0) {
nvgpu_err(g, "GPCPLL reference clock is zero");
@@ -1451,13 +1446,15 @@ void gm20b_init_clk_ops(struct gpu_ops *gops)
static int rate_get(void *data, u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
*val = (u64)gk20a_clk_get_rate(g);
struct clk_gk20a *clk = &g->clk;
*val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
return 0;
}
static int rate_set(void *data, u64 val)
{
struct gk20a *g = (struct gk20a *)data;
return gk20a_clk_set_rate(g, (u32)val);
return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val);
}
DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n");

31
drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
View File

@@ -754,6 +754,27 @@ void gk20a_tegra_init_secure_alloc(struct gk20a *g)
}
#ifdef CONFIG_COMMON_CLK
static struct clk *gk20a_clk_get(struct gk20a *g)
{
if (!g->clk.tegra_clk) {
struct clk *clk;
char clk_dev_id[32];
struct device *dev = dev_from_gk20a(g);
snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev));
clk = clk_get_sys(clk_dev_id, "gpu");
if (IS_ERR(clk)) {
nvgpu_err(g, "fail to get tegra gpu clk %s/gpu\n",
clk_dev_id);
return NULL;
}
g->clk.tegra_clk = clk;
}
return g->clk.tegra_clk;
}
static int gm20b_clk_prepare_ops(struct clk_hw *hw)
{
struct clk_gk20a *clk = to_clk_gk20a(hw);
@@ -809,6 +830,10 @@ static int gm20b_register_gpcclk(struct gk20a *g)
struct clk *c;
int err = 0;
/* make sure the clock is available */
if (!gk20a_clk_get(g))
return -ENOSYS;
err = gm20b_init_clk_setup_sw(g);
if (err)
return err;
@@ -958,7 +983,11 @@ static long gk20a_round_clk_rate(struct device *dev, unsigned long rate)
struct gk20a_platform *platform = gk20a_get_platform(dev);
struct gk20a *g = platform->g;
return gk20a_clk_round_rate(g, rate);
/* make sure the clock is available */
if (!gk20a_clk_get(g))
return rate;
return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate);
}
static int gk20a_clk_get_freqs(struct device *dev,