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gpu: nvgpu: bvec for priv_ring

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-Added BVEC coverage tests for priv_ring.
-Extended existing unit test to cover all possible equivalence classes
handling. All the classes are considered valid. Test is considered
passed as long as there are no BUGs.

Jira NVGPU-6405

Change-Id: Ia857e84c5e26856ee13d99d0c615db7f5a62e4a5
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2549223
(cherry picked from commit 1e6ffc1f3df6303c24b42534bd8b449b7b0e7677)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2556388
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Debarshi Dutta
2021-07-05 11:03:20 +05:30
committed by mobile promotions
parent c7be5e8ee1
commit c50b39f599
2 changed files with 13 additions and 2 deletions
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7
userspace/units/priv_ring/nvgpu-priv_ring.c
View File

@@ -21,6 +21,7 @@
*/ */
#include <unit/unit.h> #include <unit/unit.h>
#include <unit/utils.h>
#include <unit/io.h> #include <unit/io.h>
#include <nvgpu/posix/io.h> #include <nvgpu/posix/io.h>
#include <nvgpu/cic_mon.h> #include <nvgpu/cic_mon.h>
@@ -377,6 +378,7 @@ int test_priv_ring_isr(struct unit_module *m, struct gk20a *g, void *args)
} }
u32 error_codes[] = { u32 error_codes[] = {
0U,
0xBADF1100U, 0xBADF1100U,
0xBADF1800U, 0xBADF1800U,
0xBADF1A00U, 0xBADF1A00U,
@@ -389,6 +391,7 @@ u32 error_codes[] = {
0xBADF5100U, 0xBADF5100U,
0xBADF5500U, 0xBADF5500U,
0xBADF5600U, 0xBADF5600U,
U32_MAX,
}; };
int test_decode_error_code(struct unit_module *m, struct gk20a *g, void *args) int test_decode_error_code(struct unit_module *m, struct gk20a *g, void *args)
@@ -401,6 +404,10 @@ int test_decode_error_code(struct unit_module *m, struct gk20a *g, void *args)
g->ops.priv_ring.decode_error_code(g, error_codes[i]); g->ops.priv_ring.decode_error_code(g, error_codes[i]);
} }
/* Call priv_ring ISR randomly on the full range */
u32 random_code = get_random_u32(1, U32_MAX - 1);
g->ops.priv_ring.decode_error_code(g, random_code);
return ret; return ret;
} }

8
userspace/units/priv_ring/nvgpu-priv_ring.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -224,17 +224,21 @@ int test_priv_ring_isr(struct unit_module *m, struct gk20a *g, void *args);
* *
* Description: Verify the priv_ring.decode_error_code HAL. * Description: Verify the priv_ring.decode_error_code HAL.
* *
* Test Type: Feature, Error injection * Test Type: Feature, Error injection, Boundary Value
* *
* Targets: gops_priv_ring.decode_error_code, gp10b_decode_error_code * Targets: gops_priv_ring.decode_error_code, gp10b_decode_error_code
* *
* Input: test_priv_ring_setup() has been executed. * Input: test_priv_ring_setup() has been executed.
* Equivalence classes:
* engine_id
* - Valid : {0 - U32_MAX}
* *
* Steps: * Steps:
* - Call decode_error_code HAL with different error_codes covering all the * - Call decode_error_code HAL with different error_codes covering all the
* branches (0xBADF1xxx, 0xBADF2xxx, 0xBADF3xxx, 0xBADF5xxx). * branches (0xBADF1xxx, 0xBADF2xxx, 0xBADF3xxx, 0xBADF5xxx).
* - Include error codes with reference the largest index for each of the error * - Include error codes with reference the largest index for each of the error
* types. * types.
* - Include boundary values and one random number in between the range [0 - U32_MAX]
* *
* Output: * Output:
* - UNIT_SUCCESS * - UNIT_SUCCESS