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gpu: nvgpu: Remove phys_addr_t from common code

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Remove phys_addr_t from common code and replace it with u64. This
faciliates QNX compiling the common code since phys_addr_t is a
Linux specific type.

JIRA NVGPU-30
JIRA NVGPU-226

Change-Id: I15fe2078f9cd0b07c7e90ad6e359c493afa56714
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576432
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2017-10-10 12:13:25 -07:00
committed by mobile promotions
parent 50975dcf2a
commit c53b94f1dd
7 changed files with 9 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c
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@@ -139,7 +139,8 @@ static void gk20a_tegra_secure_destroy(struct gk20a *g,
DEFINE_DMA_ATTRS(attrs);
if (desc->mem.priv.sgt) {
phys_addr_t pa = sg_phys(desc->mem.priv.sgt->sgl);
u64 pa = nvgpu_mem_get_phys_addr(g, &desc->mem);
dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, __DMA_ATTR(attrs));
dma_free_attrs(&tegra_vpr_dev, desc->mem.size,
(void *)(uintptr_t)pa,

2
drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
View File

@@ -622,7 +622,7 @@ int gk20a_fecs_trace_bind_channel(struct gk20a *g,
u32 lo;
u32 hi;
phys_addr_t pa;
u64 pa;
struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
struct gk20a_fecs_trace *trace = g->fecs_trace;
struct nvgpu_mem *mem = &ch_ctx->gr_ctx->mem;

2
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -1289,7 +1289,7 @@ struct gk20a {
u64 dma_memory_used;
#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
phys_addr_t syncpt_unit_base;
u64 syncpt_unit_base;
size_t syncpt_unit_size;
u32 syncpt_size;
#endif

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -2104,7 +2104,7 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g)
{
struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
int retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT;
phys_addr_t inst_ptr;
u64 inst_ptr;
u32 val;
while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) &

7
drivers/gpu/nvgpu/gk20a/mm_gk20a.c
View File

@@ -1227,13 +1227,10 @@ void gk20a_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block)
u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct nvgpu_mem *inst_block)
{
u64 addr;
if (g->mm.has_physical_mode)
addr = gk20a_mem_phys(inst_block);
return nvgpu_mem_get_phys_addr(g, inst_block);
else
addr = nvgpu_mem_get_addr(g, inst_block);
return addr;
return nvgpu_mem_get_addr(g, inst_block);
}
static int gk20a_init_bar1_vm(struct mm_gk20a *mm)

15
drivers/gpu/nvgpu/gk20a/mm_gk20a.h
View File

@@ -344,21 +344,6 @@ bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g);
int gk20a_mm_mmu_vpr_info_fetch(struct gk20a *g);
static inline phys_addr_t gk20a_mem_phys(struct nvgpu_mem *mem)
{
/* FIXME: the sgt/sgl may get null if this is accessed e.g. in an isr
* during channel deletion - attempt to fix at least null derefs */
struct sg_table *sgt = mem->priv.sgt;
if (sgt) {
struct scatterlist *sgl = sgt->sgl;
if (sgl)
return sg_phys(sgl);
}
return 0;
}
u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
u64 map_offset,
struct nvgpu_sgt *sgt,

3
drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
View File

@@ -436,7 +436,8 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
u64 compbit_base_post_divide64;
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
compbit_store_iova = nvgpu_mem_get_phys_addr(g,
&gr->compbit_store.mem);
else
compbit_store_iova = nvgpu_mem_get_addr(g,
&gr->compbit_store.mem);