gpu: nvgpu: add debugger flag for hwpm_map units

Add NVGPU_DEBUGGER flag for common.gr.hwpm_map and
common.hal.gr.hwpm_map units

Jira NVGPU-3505

Change-Id: I5c9b6f98c7a8f536f5a8492febaa6140ef2adb6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130147
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile.sources

@@ -107,7 +107,6 @@ srcs += common/utils/enabled.c \
 	common/gr/gr_falcon.c \
 	common/gr/gr_config.c \
 	common/gr/gr_setup.c \
-	common/gr/hwpm_map.c \
 	common/gr/obj_ctx.c \
 	common/gr/fs_state.c \
 	common/netlist/netlist.c \
@@ -176,7 +175,6 @@ srcs += common/utils/enabled.c \
 	hal/gr/intr/gr_intr_gm20b.c \
 	hal/gr/intr/gr_intr_gp10b.c \
 	hal/gr/intr/gr_intr_gv11b.c \
-	hal/gr/hwpm_map/hwpm_map_gv100.c \
 	hal/gr/falcon/gr_falcon_gm20b.c \
 	hal/gr/falcon/gr_falcon_gp10b.c \
 	hal/gr/falcon/gr_falcon_gv11b.c \
@@ -311,11 +309,13 @@ endif
 ifeq ($(NVGPU_DEBUGGER),1)
 srcs += common/debugger.c \
 	common/regops/regops.c \
+	common/gr/hwpm_map.c \
 	hal/regops/regops_gm20b.c \
 	hal/regops/regops_gp10b.c \
 	hal/regops/regops_gv11b.c \
 	hal/regops/regops_gv100.c \
-	hal/regops/regops_tu104.c
+	hal/regops/regops_tu104.c \
+	hal/gr/hwpm_map/hwpm_map_gv100.c
 endif
 
 ifeq ($(NVGPU_FEATURE_CE),1)

drivers/gpu/nvgpu/common/gr/gr.c

@@ -284,7 +284,9 @@ static void gr_remove_support(struct gk20a *g)
 
 	nvgpu_netlist_deinit_ctx_vars(g);
 
+#ifdef NVGPU_DEBUGGER
 	nvgpu_gr_hwpm_map_deinit(g, gr->hwpm_map);
+#endif
 
 	nvgpu_gr_falcon_remove_support(g, gr->falcon);
 	gr->falcon = NULL;
@@ -401,12 +403,14 @@ static int gr_init_setup_sw(struct gk20a *g)
 		goto clean_up;
 	}
 
+#ifdef NVGPU_DEBUGGER
 	err = nvgpu_gr_hwpm_map_init(g, &g->gr->hwpm_map,
 			nvgpu_gr_falcon_get_pm_ctxsw_image_size(g->gr->falcon));
 	if (err != 0) {
 		nvgpu_err(g, "hwpm_map init failed");
 		goto clean_up;
 	}
+#endif
 
 #ifdef NVGPU_GRAPHICS
 	err = nvgpu_gr_config_init_map_tiles(g, gr->config);

drivers/gpu/nvgpu/common/gr/gr_priv.h

@@ -51,7 +51,9 @@ struct nvgpu_gr {
 
 	struct nvgpu_gr_config *config;
 
+#ifdef NVGPU_DEBUGGER
 	struct nvgpu_gr_hwpm_map *hwpm_map;
+#endif
 
 #ifdef NVGPU_GRAPHICS
 	struct nvgpu_gr_zcull *zcull;

drivers/gpu/nvgpu/common/gr/gr_utils.c

@@ -66,10 +66,12 @@ struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g)
 	return g->gr->config;
 }
 
+#ifdef NVGPU_DEBUGGER
 struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g)
 {
 	return g->gr->hwpm_map;
 }
+#endif
 
 struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c

@@ -722,12 +722,14 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
 		goto clean_up;
 	}
 
+#ifdef NVGPU_DEBUGGER
 	err = nvgpu_gr_hwpm_map_init(g, &g->gr->hwpm_map,
 			nvgpu_gr_falcon_get_pm_ctxsw_image_size(g->gr->falcon));
 	if (err != 0) {
 		nvgpu_err(g, "hwpm_map init failed");
 		goto clean_up;
 	}
+#endif
 
 #ifdef NVGPU_GRAPHICS
 	err = vgpu_gr_init_gr_zcull(g, gr,

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -326,10 +326,12 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 			.program_zcull_mapping = NULL,
 		},
 #endif /* NVGPU_GRAPHICS */
+#ifdef NVGPU_DEBUGGER
 		.hwpm_map = {
 			.align_regs_perf_pma =
 				gv100_gr_hwpm_map_align_regs_perf_pma,
 		},
+#endif
 		.falcon = {
 			.init_ctx_state = vgpu_gr_init_ctx_state,
 			.load_ctxsw_ucode = NULL,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -448,10 +448,12 @@ static const struct gpu_ops gv11b_ops = {
 			.program_zcull_mapping = gv11b_gr_program_zcull_mapping,
 		},
 #endif /* NVGPU_GRAPHICS */
+#ifdef NVGPU_DEBUGGER
 		.hwpm_map = {
 			.align_regs_perf_pma =
 				gv100_gr_hwpm_map_align_regs_perf_pma,
 		},
+#endif
 		.init = {
 			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.get_nonpes_aware_tpc =

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -482,12 +482,14 @@ static const struct gpu_ops tu104_ops = {
 			.program_zcull_mapping = gv11b_gr_program_zcull_mapping,
 		},
 #endif /* NVGPU_GRAPHICS */
+#ifdef NVGPU_DEBUGGER
 		.hwpm_map = {
 			.align_regs_perf_pma =
 				gv100_gr_hwpm_map_align_regs_perf_pma,
 			.get_active_fbpa_mask =
 				gv100_gr_hwpm_map_get_active_fbpa_mask,
 		},
+#endif
 		.init = {
 			.get_no_of_sm = nvgpu_gr_get_no_of_sm,
 			.get_nonpes_aware_tpc =

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -662,10 +662,12 @@ struct gpu_ops {
 		} zcull;
 #endif /* NVGPU_GRAPHICS */
 
+#ifdef NVGPU_DEBUGGER
 		struct {
 			void (*align_regs_perf_pma)(u32 *offset);
 			u32 (*get_active_fbpa_mask)(struct gk20a *g);
 		} hwpm_map;
+#endif
 
 		struct {
 			u32 (*get_no_of_sm)(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h

@@ -45,7 +45,9 @@ struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g);
 struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g);
 #endif
 struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g);
+#ifdef NVGPU_DEBUGGER
 struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g);
+#endif
 struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g);
 #ifdef CONFIG_GK20A_CTXSW_TRACE
 struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr(