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gpu: nvgpu: runlist MISRA fixes for Rule 10.3

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Using u32 with bitops like for_each_set_bit results in MISRA
violation as bitops internally uses unsigned long.
Define tsgid as unsigned long an use (u32) cast when needed.

Jira NVGPU-3379

Change-Id: I99f9dae18ee74223de40dd5990bfad4eee2f4559
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109680
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-05-01 13:46:02 -07:00
committed by mobile promotions
parent 8052ce1d9f
commit c5f873fa31
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/nvgpu/common/fifo/runlist.c
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@@ -134,7 +134,7 @@ static u32 nvgpu_runlist_append_prio(struct fifo_gk20a *f,
nvgpu_log_fn(f->g, " ");
for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) {
struct tsg_gk20a *tsg = nvgpu_tsg_get_from_id(f->g, tsgid);
struct tsg_gk20a *tsg = nvgpu_tsg_get_from_id(f->g, (u32)tsgid);
u32 entries;
if (tsg->interleave_level == interleave_level) {
@@ -177,7 +177,7 @@ static u32 nvgpu_runlist_append_med(struct fifo_gk20a *f,
nvgpu_log_fn(f->g, " ");
for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) {
struct tsg_gk20a *tsg = nvgpu_tsg_get_from_id(f->g, tsgid);
struct tsg_gk20a *tsg = nvgpu_tsg_get_from_id(f->g, (u32)tsgid);
u32 entries;
if (tsg->interleave_level !=
@@ -216,7 +216,7 @@ static u32 nvgpu_runlist_append_low(struct fifo_gk20a *f,
nvgpu_log_fn(f->g, " ");
for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) {
struct tsg_gk20a *tsg = nvgpu_tsg_get_from_id(f->g, tsgid);
struct tsg_gk20a *tsg = nvgpu_tsg_get_from_id(f->g, (u32)tsgid);
u32 entries;
if (tsg->interleave_level !=