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gpu: nvgpu: fix misra rule 3.1 violation

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With http path for ECC hw ref manual specified with two forward slashes
within comment block rule 3.1 is violated.

We can specify the http path with single forward slash. Fix it.

Change-Id: I310869995e1d064b4216a3ed99ea57f78cf78d8d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2614150
Reviewed-by: V M S Seeta Rama Raju Mudundi <srajum@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 0e1cb893d2637badece8d39f93f4025e92d8bd8e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2706558
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2021-10-21 09:41:12 +05:30
committed by mobile promotions
parent d82400d2b8
commit c7d495ffd6
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
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@@ -52,7 +52,7 @@ struct gops_ltc_intr {
* - For each ltc slice \a slice from 0 to g->ltc->slices_per_ltc - 1: * - For each ltc slice \a slice from 0 to g->ltc->slices_per_ltc - 1:
* -# The L2 has SEC-DED protection on its data RAM and parity protection on the * -# The L2 has SEC-DED protection on its data RAM and parity protection on the
* byte enables RAM. * byte enables RAM.
* -# See <a href="https:/p4viewer.nvidia.com/get//hw/doc/gpu/ampere/ampere/design/Functional_Descriptions/Resiliency/Ampere_gpu_resiliency_ECC.docx</a> for details. * -# See <a href="https:/p4viewer.nvidia.com/get/hw/doc/gpu/ampere/ampere/design/Functional_Descriptions/Resiliency/Ampere_gpu_resiliency_ECC.doc">Ampere_gpu_resiliency_ECC.doc</a> for details.
* -# Following PRI registers are used for controlling parity ECC and * -# Following PRI registers are used for controlling parity ECC and
* getting the status and information of ECC. * getting the status and information of ECC.
* -# Control: * -# Control: