gpu: nvgpu: move ch and tsg specific ctxsw timeout

Move check_ch_ctxsw_timeout under channel ops as
check_ctxsw_timeout

Move check_tsg_ctxsw_timeout under tsg ops as
check_ctxsw_timeout

JIRA NVGPU-1312

Change-Id: If1711769176e4ee5945a00a61eab7bd67f6f665d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076826
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -425,8 +425,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.tsg_unbind_channel = vgpu_tsg_unbind_channel,
 		.post_event_id = gk20a_tsg_event_id_post_event,
 		.ch_abort_clean_up = gk20a_channel_abort_clean_up,
-		.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
-		.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
@@ -507,6 +505,10 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.enable = vgpu_channel_enable,
 		.disable = vgpu_channel_disable,
 		.count = vgpu_channel_count,
+		.check_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
+	},
+	.tsg = {
+		.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
 	},
 	.netlist = {
 		.get_netlist_name = gp10b_netlist_get_name,
@@ -724,6 +726,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 	gops->runlist = vgpu_gp10b_ops.runlist;
 	gops->userd = vgpu_gp10b_ops.userd;
 	gops->channel = vgpu_gp10b_ops.channel;
+	gops->tsg = vgpu_gp10b_ops.tsg;
 	gops->sync = vgpu_gp10b_ops.sync;
 	gops->engine_status = vgpu_gp10b_ops.engine_status;
 	gops->pbdma_status = vgpu_gp10b_ops.pbdma_status;

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -501,8 +501,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.tsg_unbind_channel = vgpu_tsg_unbind_channel,
 		.post_event_id = gk20a_tsg_event_id_post_event,
 		.ch_abort_clean_up = gk20a_channel_abort_clean_up,
-		.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
-		.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
@@ -588,6 +586,10 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.enable = vgpu_channel_enable,
 		.disable = vgpu_channel_disable,
 		.count = vgpu_channel_count,
+		.check_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
+	},
+	.tsg = {
+		.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
 	},
 	.netlist = {
 		.get_netlist_name = gv11b_netlist_get_name,
@@ -807,6 +809,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 	gops->runlist = vgpu_gv11b_ops.runlist;
 	gops->userd = vgpu_gv11b_ops.userd;
 	gops->channel = vgpu_gv11b_ops.channel;
+	gops->tsg = vgpu_gv11b_ops.tsg;
 	gops->sync = vgpu_gv11b_ops.sync;
 	gops->engine_status = vgpu_gv11b_ops.engine_status;
 	gops->pbdma_status = vgpu_gv11b_ops.pbdma_status;

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -1231,12 +1231,12 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g)
 		}
 
 		if (is_tsg) {
-			ret = nvgpu_tsg_check_ctxsw_timeout(
+			ret = g->ops.tsg.check_ctxsw_timeout(
 					&f->tsg[id], &verbose, &ms);
 		} else {
 			ch = gk20a_channel_from_id(g, id);
 			if (ch != NULL) {
-				ret = g->ops.fifo.check_ch_ctxsw_timeout(
+				ret = g->ops.channel.check_ctxsw_timeout(
 					ch, &verbose, &ms);
 
 				gk20a_channel_put(ch);

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -574,8 +574,6 @@ static const struct gpu_ops gm20b_ops = {
 		.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
 		.post_event_id = gk20a_tsg_event_id_post_event,
 		.ch_abort_clean_up = gk20a_channel_abort_clean_up,
-		.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
-		.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
@@ -665,6 +663,10 @@ static const struct gpu_ops gm20b_ops = {
 		.count = gm20b_channel_count,
 		.read_state = gk20a_channel_read_state,
 		.force_ctx_reload = gm20b_channel_force_ctx_reload,
+		.check_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
+	},
+	.tsg = {
+		.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
 	},
 	.netlist = {
 		.get_netlist_name = gm20b_netlist_get_name,
@@ -930,6 +932,7 @@ int gm20b_init_hal(struct gk20a *g)
 	gops->runlist = gm20b_ops.runlist;
 	gops->userd = gm20b_ops.userd;
 	gops->channel = gm20b_ops.channel;
+	gops->tsg = gm20b_ops.tsg;
 	gops->sync = gm20b_ops.sync;
 	gops->engine_status = gm20b_ops.engine_status;
 	gops->pbdma_status = gm20b_ops.pbdma_status;

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -652,8 +652,6 @@ static const struct gpu_ops gp10b_ops = {
 		.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
 		.post_event_id = gk20a_tsg_event_id_post_event,
 		.ch_abort_clean_up = gk20a_channel_abort_clean_up,
-		.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
-		.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier,
@@ -746,6 +744,10 @@ static const struct gpu_ops gp10b_ops = {
 		.count = gm20b_channel_count,
 		.read_state = gk20a_channel_read_state,
 		.force_ctx_reload = gm20b_channel_force_ctx_reload,
+		.check_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
+	},
+	.tsg = {
+		.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
 	},
 	.netlist = {
 		.get_netlist_name = gp10b_netlist_get_name,
@@ -1017,6 +1019,7 @@ int gp10b_init_hal(struct gk20a *g)
 	gops->runlist = gp10b_ops.runlist;
 	gops->userd = gp10b_ops.userd;
 	gops->channel = gp10b_ops.channel;
+	gops->tsg = gp10b_ops.tsg;
 	gops->sync = gp10b_ops.sync;
 	gops->engine_status = gp10b_ops.engine_status;
 	gops->pbdma_status = gp10b_ops.pbdma_status;

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -831,8 +831,6 @@ static const struct gpu_ops gv100_ops = {
 		.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
 		.post_event_id = gk20a_tsg_event_id_post_event,
 		.ch_abort_clean_up = gk20a_channel_abort_clean_up,
-		.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
-		.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier_if_empty,
@@ -928,6 +926,10 @@ static const struct gpu_ops gv100_ops = {
 		.read_state = gv11b_channel_read_state,
 		.force_ctx_reload = gm20b_channel_force_ctx_reload,
 		.reset_faulted = gv11b_channel_reset_faulted,
+		.check_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
+	},
+	.tsg = {
+		.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
 	},
 	.netlist = {
 		.get_netlist_name = gv100_netlist_get_name,
@@ -1311,6 +1313,7 @@ int gv100_init_hal(struct gk20a *g)
 	gops->runlist = gv100_ops.runlist;
 	gops->userd = gv100_ops.userd;
 	gops->channel = gv100_ops.channel;
+	gops->tsg = gv100_ops.tsg;
 	gops->sync = gv100_ops.sync;
 	gops->engine_status = gv100_ops.engine_status;
 	gops->pbdma_status = gv100_ops.pbdma_status;

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -786,8 +786,6 @@ static const struct gpu_ops gv11b_ops = {
 		.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
 		.post_event_id = gk20a_tsg_event_id_post_event,
 		.ch_abort_clean_up = gk20a_channel_abort_clean_up,
-		.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
-		.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier_if_empty,
@@ -886,6 +884,10 @@ static const struct gpu_ops gv11b_ops = {
 		.read_state = gv11b_channel_read_state,
 		.force_ctx_reload = gm20b_channel_force_ctx_reload,
 		.reset_faulted = gv11b_channel_reset_faulted,
+		.check_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
+	},
+	.tsg = {
+		.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
 	},
 	.netlist = {
 		.get_netlist_name = gv11b_netlist_get_name,
@@ -1182,6 +1184,7 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->runlist = gv11b_ops.runlist;
 	gops->userd = gv11b_ops.userd;
 	gops->channel = gv11b_ops.channel;
+	gops->tsg = gv11b_ops.tsg;
 	gops->sync = gv11b_ops.sync;
 	gops->engine_status = gv11b_ops.engine_status;
 	gops->pbdma_status = gv11b_ops.pbdma_status;

drivers/gpu/nvgpu/hal/fifo/fifo_intr_gv11b.c

@@ -326,7 +326,7 @@ bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr)
 				continue;
 			}
 
-			if (nvgpu_tsg_check_ctxsw_timeout(
+			if (g->ops.tsg.check_ctxsw_timeout(
 				&f->tsg[tsgid], &verbose, &ms)) {
 				ret = true;
 

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -925,10 +925,6 @@ struct gpu_ops {
 		u32 (*get_preempt_timeout)(struct gk20a *g);
 		void (*post_event_id)(struct tsg_gk20a *tsg, int event_id);
 		void (*ch_abort_clean_up)(struct channel_gk20a *ch);
-		bool (*check_tsg_ctxsw_timeout)(struct tsg_gk20a *tsg,
-						bool *verbose, u32 *ms);
-		bool (*check_ch_ctxsw_timeout)(struct channel_gk20a *ch,
-						bool *verbose, u32 *ms);
 		int (*channel_suspend)(struct gk20a *g);
 		int (*channel_resume)(struct gk20a *g);
 		void (*set_error_notifier)(struct channel_gk20a *ch, u32 error);
@@ -1046,7 +1042,13 @@ struct gpu_ops {
 		void (*force_ctx_reload)(struct channel_gk20a *ch);
 		void (*reset_faulted)(struct gk20a *g, struct channel_gk20a *ch,
 				bool eng, bool pbdma);
+		bool (*check_ctxsw_timeout)(struct channel_gk20a *ch,
+					bool *verbose, u32 *ms);
 	} channel;
+	struct {
+		bool (*check_ctxsw_timeout)(struct tsg_gk20a *tsg,
+					bool *verbose, u32 *ms);
+	} tsg;
 	struct {
 		void (*read_engine_status_info) (struct gk20a *g,
 			u32 engine_id, struct nvgpu_engine_status_info *status);

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -866,8 +866,6 @@ static const struct gpu_ops tu104_ops = {
 		.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
 		.post_event_id = gk20a_tsg_event_id_post_event,
 		.ch_abort_clean_up = gk20a_channel_abort_clean_up,
-		.check_tsg_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
-		.check_ch_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
 		.channel_suspend = gk20a_channel_suspend,
 		.channel_resume = gk20a_channel_resume,
 		.set_error_notifier = nvgpu_set_error_notifier_if_empty,
@@ -966,6 +964,10 @@ static const struct gpu_ops tu104_ops = {
 		.read_state = gv11b_channel_read_state,
 		.force_ctx_reload = gm20b_channel_force_ctx_reload,
 		.reset_faulted = gv11b_channel_reset_faulted,
+		.check_ctxsw_timeout = nvgpu_channel_check_ctxsw_timeout,
+	},
+	.tsg = {
+		.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,
 	},
 	.netlist = {
 		.get_netlist_name = tu104_netlist_get_name,
@@ -1355,6 +1357,7 @@ int tu104_init_hal(struct gk20a *g)
 	gops->runlist = tu104_ops.runlist;
 	gops->userd = tu104_ops.userd;
 	gops->channel = tu104_ops.channel;
+	gops->tsg = tu104_ops.tsg;
 	gops->sync = tu104_ops.sync;
 	gops->engine_status = tu104_ops.engine_status;
 	gops->pbdma_status = tu104_ops.pbdma_status;