nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: volt: Remove usused code in volt_rail

Browse Source 
- Removed conditional checks for split rails
- Removed macro of split rail

Change-Id: Id14eeabdbbfb4e7adc516a5631eedee7a92427da
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243071
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2019-11-20 12:25:10 +05:30
committed by Alex Waterman
parent 4c1618cc52
commit c83c730c30
2 changed files with 12 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
View File

@@ -469,50 +469,24 @@ int nvgpu_volt_rail_pmu_setup(struct gk20a *g)
u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
u8 vbios_volt_domain)
{
switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
if (vbios_volt_domain == 0U) {
return CTRL_VOLT_DOMAIN_LOGIC;
}
break;
case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
if (vbios_volt_domain == 0U) {
return CTRL_VOLT_DOMAIN_LOGIC;
} else if (vbios_volt_domain == 1U) {
return CTRL_VOLT_DOMAIN_SRAM;
} else {
nvgpu_info(g, "Split Rail has invalid entry");
}
break;
default:
nvgpu_info(g, "Volt domain is invalid");
break;
}
if (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal ==
CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) {
return CTRL_VOLT_DOMAIN_LOGIC;
} else {
nvgpu_err(g, "Unsupported volt domain hal");
return CTRL_VOLT_DOMAIN_INVALID;
}
}
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
{
switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) {
return 0U;
}
break;
case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) {
return 0U;
} else if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) {
return 1U;
} else {
nvgpu_info(g, "Split Rail has invalid entry");
}
break;
default:
nvgpu_info(g, "Boardobj IDX is invalid");
break;
}
if (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal ==
CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL) {
return 0U;
} else {
nvgpu_err(g, "Unsupported volt domain hal");
return CTRL_BOARDOBJ_IDX_INVALID;
}
}
int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail

1
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlvolt.h
View File

@@ -41,7 +41,6 @@
* Macros for Voltage Domain HAL.
*/
#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01U
/*
* Macros for Voltage Domains.