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gpu: nvgpu: rename mem_desc to nvgpu_mem

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$ find -type f | \
  xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g'

JIRA NVGPU-12

Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1326194
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2017-03-22 10:01:14 -07:00
committed by mobile promotions
parent 633d331ae2
commit c876bec8ba
5 changed files with 14 additions and 14 deletions
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6
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -112,7 +112,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
unsigned long acquire_timeout, u32 flags)
{
struct gk20a *g = c->g;
struct mem_desc *mem = &c->inst_block;
struct nvgpu_mem *mem = &c->inst_block;
u32 data;
gk20a_dbg_fn("");
@@ -193,7 +193,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c)
{
struct mem_desc *userd_mem = &g->fifo.userd;
struct nvgpu_mem *userd_mem = &g->fifo.userd;
u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32));
return nvgpu_mem_rd32(g, userd_mem,
@@ -202,7 +202,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c)
static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c)
{
struct mem_desc *userd_mem = &g->fifo.userd;
struct nvgpu_mem *userd_mem = &g->fifo.userd;
u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32));
nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(),

12
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -642,7 +642,7 @@ static int gr_gv11b_init_ctx_state(struct gk20a *g)
}
int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size,
struct mem_desc *mem)
struct nvgpu_mem *mem)
{
int err;
@@ -778,7 +778,7 @@ fail_free_gk20a_ctx:
static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
struct gr_ctx_desc *gr_ctx)
{
struct mem_desc *mem = &gr_ctx->mem;
struct nvgpu_mem *mem = &gr_ctx->mem;
if (nvgpu_mem_begin(g, mem)) {
WARN_ON("Cannot map context");
@@ -834,7 +834,7 @@ static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
struct channel_ctx_gk20a *ch_ctx,
struct mem_desc *mem)
struct nvgpu_mem *mem)
{
struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
u32 gfxp_preempt_option =
@@ -1925,7 +1925,7 @@ static int gr_gv11b_commit_global_timeslice(struct gk20a *g,
}
static void gv11b_restore_context_header(struct gk20a *g,
struct mem_desc *ctxheader)
struct nvgpu_mem *ctxheader)
{
u32 va_lo, va_hi;
struct gr_gk20a *gr = &g->gr;
@@ -1947,7 +1947,7 @@ static void gv11b_restore_context_header(struct gk20a *g,
ctxsw_prog_main_image_num_save_ops_o(), 0);
}
static void gr_gv11b_write_zcull_ptr(struct gk20a *g,
struct mem_desc *mem, u64 gpu_va)
struct nvgpu_mem *mem, u64 gpu_va)
{
u32 va_lo, va_hi;
@@ -1962,7 +1962,7 @@ static void gr_gv11b_write_zcull_ptr(struct gk20a *g,
static void gr_gv11b_write_pm_ptr(struct gk20a *g,
struct mem_desc *mem, u64 gpu_va)
struct nvgpu_mem *mem, u64 gpu_va)
{
u32 va_lo, va_hi;

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -44,7 +44,7 @@ enum {
void gv11b_init_gr(struct gpu_ops *ops);
int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size,
struct mem_desc *mem);
struct nvgpu_mem *mem);
/*zcull*/
void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
u32 *zcull_map_tiles);

2
drivers/gpu/nvgpu/gv11b/mm_gv11b.c
View File

@@ -28,7 +28,7 @@ static bool gv11b_mm_is_bar1_supported(struct gk20a *g)
return false;
}
static void gv11b_init_inst_block(struct mem_desc *inst_block,
static void gv11b_init_inst_block(struct nvgpu_mem *inst_block,
struct vm_gk20a *vm, u32 big_page_size)
{
struct gk20a *g = gk20a_from_vm(vm);

6
drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
View File

@@ -24,7 +24,7 @@
#include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h>
static void gv11b_init_subcontext_pdb(struct channel_gk20a *c,
struct mem_desc *inst_block);
struct nvgpu_mem *inst_block);
void gv11b_free_subctx_header(struct channel_gk20a *c)
{
@@ -86,7 +86,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c)
}
static void gv11b_init_subcontext_pdb(struct channel_gk20a *c,
struct mem_desc *inst_block)
struct nvgpu_mem *inst_block)
{
struct gk20a *g = c->g;
struct vm_gk20a *vm;
@@ -126,7 +126,7 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c,
int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va)
{
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct mem_desc *gr_mem;
struct nvgpu_mem *gr_mem;
struct gk20a *g = c->g;
int ret = 0;
u32 addr_lo, addr_hi;