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gpu: nvgpu: fix MISRA Rule 2.2 no dead code

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MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.

This patch fixes some of these reported violations.

Jira NVGPU-858

Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-05-02 08:45:20 -07:00
committed by mobile promotions
parent 9a450fe2bf
commit c90fcbae2a
6 changed files with 11 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/ce/ce.c
View File

@@ -531,7 +531,6 @@ u32 nvgpu_ce_create_context(struct gk20a *g,
ce_ctx->tsg = nvgpu_tsg_open(g, nvgpu_current_pid(g));
if (ce_ctx->tsg == NULL) {
nvgpu_err(g, "ce: gk20a tsg not available");
err = -ENOMEM;
goto end;
}
@@ -543,7 +542,6 @@ u32 nvgpu_ce_create_context(struct gk20a *g,
nvgpu_current_pid(g), nvgpu_current_tid(g));
if (ce_ctx->ch == NULL) {
nvgpu_err(g, "ce: gk20a channel not available");
err = -ENOMEM;
goto end;
}
ce_ctx->ch->wdt.enabled = false;

3
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -52,9 +52,8 @@
bool is_nvgpu_gpu_state_valid(struct gk20a *g)
{
u32 boot_0 = 0xffffffffU;
u32 boot_0 = nvgpu_mc_boot_0(g, NULL, NULL, NULL);
boot_0 = nvgpu_mc_boot_0(g, NULL, NULL, NULL);
if (boot_0 == 0xffffffffU) {
nvgpu_err(g, "GPU has disappeared from bus!!");
return false;

1
drivers/gpu/nvgpu/common/mm/vm.c
View File

@@ -1313,7 +1313,6 @@ static int nvgpu_vm_compute_compression(struct vm_gk20a *vm,
"Unsupported page size for compressible "
"kind, demoting to incompressible");
binfo->compr_kind = NVGPU_KIND_INVALID;
kind_compressible = false;
}
}

10
drivers/gpu/nvgpu/common/pmu/clk/clk.c
View File

@@ -244,18 +244,12 @@ done:
int nvgpu_clk_get_fll_clks(struct gk20a *g,
struct nvgpu_set_fll_clk *setfllclk)
{
int status = -EINVAL;
status = g->pmu.clk_pmu->get_fll(g, setfllclk);
return status;
return g->pmu.clk_pmu->get_fll(g, setfllclk);
}
int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
{
int status = -EINVAL;
status = g->pmu.clk_pmu->set_boot_fll(g);
return status;
return g->pmu.clk_pmu->set_boot_fll(g);
}
int nvgpu_clk_init_pmupstate(struct gk20a *g)

2
drivers/gpu/nvgpu/common/pmu/ipc/pmu_cmd.c
View File

@@ -246,7 +246,7 @@ static int pmu_cmd_payload_setup_rpc(struct gk20a *g, struct pmu_cmd *cmd,
nvgpu_memcpy((u8 *)
nvgpu_engine_fb_queue_get_work_buffer(queue) +
alloc.dmem_offset,
(u8 *)payload->rpc.prpc, payload->rpc.size_rpc);
(u8 *)payload->rpc.prpc, alloc.dmem_size);
alloc.dmem_offset += nvgpu_pmu_seq_get_fbq_heap_offset(seq);

9
drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
View File

@@ -186,8 +186,8 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
u8 *pwr_topology_table_ptr = NULL;
u8 *curr_pwr_topology_table_ptr = NULL;
struct boardobj *boardobj;
struct pwr_topology_2x_header pwr_topology_table_header = { 0 };
struct pwr_topology_2x_entry pwr_topology_table_entry = { 0 };
struct pwr_topology_2x_header pwr_topology_table_header;
struct pwr_topology_2x_entry pwr_topology_table_entry;
u32 index;
u32 obj_index = 0;
size_t pwr_topology_size;
@@ -197,6 +197,11 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
struct pwr_channel_sensor sensor;
} pwr_topology_data;
(void) memset(&pwr_topology_table_header, 0U,
sizeof(struct pwr_topology_2x_header));
(void) memset(&pwr_topology_table_entry, 0U,
sizeof(struct pwr_topology_2x_entry));
nvgpu_log_info(g, " ");
pwr_topology_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,