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gpu: nvgpu: preempt MISRA fix for Rule 17.7

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Check return value of nvgpu_pmu_lock_rlease and
spit error message.
Check return value of nvgpu_timeout_init and spit
error message. Also return to the calling function
upon timeout init error.

JIRA NVGPU-3383

Change-Id: I91636255d1f16fab4b2ab934df67149f5efca7fe
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113107
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-05-06 11:22:51 -07:00
committed by mobile promotions
parent 1639db51b2
commit c9686156c1
1 changed files with 16 additions and 4 deletions
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20
drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c
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@@ -67,10 +67,16 @@ int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
{
struct nvgpu_timeout timeout;
u32 delay = POLL_DELAY_MIN_US;
int ret = -EBUSY;
int ret;
nvgpu_timeout_init(g, &timeout, nvgpu_preempt_get_timeout(g),
ret = nvgpu_timeout_init(g, &timeout, nvgpu_preempt_get_timeout(g),
NVGPU_TIMER_CPU_TIMER);
if (ret != 0) {
nvgpu_err(g, "timeout_init failed: %d", ret);
return ret;
}
ret = -EBUSY;
do {
if ((nvgpu_readl(g, fifo_preempt_r()) &
fifo_preempt_pending_true_f()) == 0U) {
@@ -106,7 +112,10 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch)
ret = gk20a_fifo_preempt_locked(g, ch->chid, ID_TYPE_CHANNEL);
if (mutex_ret == 0) {
nvgpu_pmu_lock_release(g, &g->pmu, PMU_MUTEX_ID_FIFO, &token);
if (nvgpu_pmu_lock_release(g, &g->pmu,
PMU_MUTEX_ID_FIFO, &token) != 0) {
nvgpu_err(g, "failed to release PMU lock");
}
}
nvgpu_runlist_unlock_active_runlists(g);
@@ -151,7 +160,10 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg)
ret = gk20a_fifo_preempt_locked(g, tsg->tsgid, ID_TYPE_TSG);
if (mutex_ret == 0) {
nvgpu_pmu_lock_release(g, &g->pmu, PMU_MUTEX_ID_FIFO, &token);
if (nvgpu_pmu_lock_release(g, &g->pmu,
PMU_MUTEX_ID_FIFO, &token) != 0) {
nvgpu_err(g, "failed to release PMU lock");
}
}
nvgpu_runlist_unlock_active_runlists(g);