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gpu: nvgpu: channel MISRA fix for Rule 17.7

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Check return value and nvgpu_assert for
g->ops.mm.cache.fb_flush(g)

JIRA NVGPU-3388

Change-Id: I24ccc4ae57a2827423db4eb96726a0fe5a7f04df
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115754
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-05-09 09:38:16 -07:00
committed by mobile promotions
parent c2b3da8e47
commit c986b60c6f
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/nvgpu/common/fifo/channel.c
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@@ -2484,7 +2484,7 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events)
* Ensure that all pending writes are actually done before trying to
* read semaphore values from DRAM.
*/
g->ops.mm.cache.fb_flush(g);
nvgpu_assert(g->ops.mm.cache.fb_flush(g) == 0);
for (chid = 0; chid < f->num_channels; chid++) {
struct nvgpu_channel *c = g->fifo.channel+chid;