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gpu: nvgpu: remove uneeded seq_desc, msg parameter of sec2_cmd_post and callback
These parameters are not required. Removing those will simplify the refactoring of the IPC units. The plan is to keep access to sequence struct members within IPC units. JIRA NVGPU-2075 Change-Id: Idf62082152448230d286cfc5e7249c9886d8251a Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085747 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -136,7 +136,7 @@ int nvgpu_sec2_destroy(struct gk20a *g)
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/* LSF's bootstrap command */
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static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g,
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struct nv_flcn_msg_sec2 *msg,
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void *param, u32 handle, u32 status)
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void *param, u32 status)
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{
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bool *command_ack = param;
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@@ -156,7 +156,6 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
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{
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struct nv_flcn_cmd_sec2 cmd;
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bool command_ack;
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u32 seq = 0;
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int err = 0;
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size_t tmp_size;
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@@ -179,8 +178,8 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
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falcon_id);
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command_ack = false;
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err = nvgpu_sec2_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_HPQ,
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sec2_handle_lsfm_boot_acr_msg, &command_ack, &seq, U32_MAX);
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err = nvgpu_sec2_cmd_post(g, &cmd, PMU_COMMAND_QUEUE_HPQ,
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sec2_handle_lsfm_boot_acr_msg, &command_ack, U32_MAX);
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if (err != 0) {
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nvgpu_err(g, "command post failed");
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}
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