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gpu: nvgpu: ga10b: move grmgr.load_timestamp_prod HAL

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The timestamp control register in the SMCARB should be configured to have
the NV_PSMCARB_TIMESTAMP_CTRL_DISABLE_TICK field cleared, otherwise the PTIMER
ticks will not be sent to GR engine.  Hence, remove the pre-processor checks
around grmgr.load_timestamp_prod call.

Bug 3510460
Bug 3500065

Change-Id: I223cea1aca28a9215287f540eb961a16e3fe6626
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671021
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2022-02-16 17:37:44 +00:00
committed by mobile promotions
parent 19a3b86f06
commit ca27a7d841
6 changed files with 2 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/grmgr/grmgr.c
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@@ -42,11 +42,9 @@ int nvgpu_init_gr_manager(struct gk20a *g)
int err = 0; int err = 0;
const struct nvgpu_device *gr_dev = NULL; const struct nvgpu_device *gr_dev = NULL;
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
if (g->ops.grmgr.load_timestamp_prod != NULL) { if (g->ops.grmgr.load_timestamp_prod != NULL) {
g->ops.grmgr.load_timestamp_prod(g); g->ops.grmgr.load_timestamp_prod(g);
} }
#endif
/* Number of gpu instance is 1 for legacy mode */ /* Number of gpu instance is 1 for legacy mode */
g->mig.max_gpc_count = g->ops.top.get_max_gpc_count(g); g->mig.max_gpc_count = g->ops.top.get_max_gpc_count(g);
nvgpu_assert(g->mig.max_gpc_count > 0U); nvgpu_assert(g->mig.max_gpc_count > 0U);

2
drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
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@@ -955,7 +955,6 @@ int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g) void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g)
{ {
u32 reg_val; u32 reg_val;
@@ -968,7 +967,6 @@ void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g)
nvgpu_writel(g, smcarb_timestamp_ctrl_r(), reg_val); nvgpu_writel(g, smcarb_timestamp_ctrl_r(), reg_val);
} }
#endif
int ga10b_grmgr_discover_gpc_ids(struct gk20a *g, int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
u32 num_gpc, struct nvgpu_gpc *gpcs) u32 num_gpc, struct nvgpu_gpc *gpcs)

2
drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
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@@ -42,9 +42,7 @@ int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
void ga10b_grmgr_get_gpcgrp_count(struct gk20a *g); void ga10b_grmgr_get_gpcgrp_count(struct gk20a *g);
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g); void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g);
#endif
int ga10b_grmgr_discover_gpc_ids(struct gk20a *g, int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
u32 num_gpc, struct nvgpu_gpc *gpcs); u32 num_gpc, struct nvgpu_gpc *gpcs);

2
drivers/gpu/nvgpu/hal/init/hal_ga100.c
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@@ -1728,9 +1728,7 @@ static const struct gops_grmgr ga100_ops_grmgr = {
#else #else
.init_gr_manager = nvgpu_init_gr_manager, .init_gr_manager = nvgpu_init_gr_manager,
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod, .load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
#endif
.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids, .discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
}; };
#endif #endif

2
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
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@@ -1707,9 +1707,7 @@ static const struct gops_grmgr ga10b_ops_grmgr = {
#else #else
.init_gr_manager = nvgpu_init_gr_manager, .init_gr_manager = nvgpu_init_gr_manager,
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod, .load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
#endif
.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids, .discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
}; };

4
drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -85,8 +85,8 @@ struct gops_grmgr {
u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id); u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id);
int (*get_mig_gpu_instance_config)(struct gk20a *g, int (*get_mig_gpu_instance_config)(struct gk20a *g,
const char **config_name, u32 *num_config_supported); const char **config_name, u32 *num_config_supported);
void (*load_timestamp_prod)(struct gk20a *g);
#endif #endif
void (*load_timestamp_prod)(struct gk20a *g);
}; };
#endif /* NVGPU_GOPS_GRMGR_H */ #endif /* NVGPU_GOPS_GRMGR_H */