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gpu: nvgpu: gops: mc: add doxygen for ltc_isr
Add doxygen for mc.ltc_isr, since it is getting called from fusa code. Jira NVGPU-6182 Change-Id: I1995cb6a2caef11f0b982b76b5dcd8d809d78a44 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> (cherry picked from commit 8ddc5e9dbbe7d711baafe1e824111010fcc969fb) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488417 GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -200,7 +200,22 @@ struct gops_mc {
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bool (*is_stall_and_eng_intr_pending)(struct gk20a *g,
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u32 engine_id, u32 *eng_intr_pending);
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/**
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* @brief Interrupt Service Routine (ISR) for handling the Level Two
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* Cache (LTC) interrupts.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked to handle the LTC interrupts from
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* #isr_stall.
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*
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* Steps:
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* - Read mc_intr_ltc_r register to get the interrupts status for LTCs.
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* - For each ltc from index 0 to nvgpu_ltc_get_ltc_count(\a g)
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* - If interrupt bitmask is set in the interrupts status register
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* - Invoke g->ops.ltc.intr.isr.
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*/
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void (*ltc_isr)(struct gk20a *g);
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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@@ -252,23 +267,6 @@ struct gops_mc {
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void (*fbpa_isr)(struct gk20a *g);
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#endif
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/**
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* @brief Interrupt Service Routine (ISR) for handling the Level Two
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* Cache (LTC) interrupts.
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*
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* @param g [in] The GPU driver struct.
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*
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* This function is invoked to handle the LTC interrupts from
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* #isr_stall.
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*
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* Steps:
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* - Read mc_intr_ltc_r register to get the interrupts status for LTCs.
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* - For each ltc from index 0 to nvgpu_ltc_get_ltc_count(\a g)
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* - If interrupt bitmask is set in the interrupts status register
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* - Invoke g->ops.ltc.intr.isr.
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*/
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void (*ltc_isr)(struct gk20a *g);
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#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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#include "include/nvgpu/nvgpu_next_gops_mc.h"
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#endif
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