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gpu: nvgpu: Fix MISRA 16.x violations in nvlink

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All the 16.x MISRA rules are relevant to switch statement
formatting and hence addressed in single patch

As per MISRA 16.1, all switch statements should be well formatted.

16.3 fixes:
Add unconditional break statements to all the switch-clauses
to adhere to MISRA rule 16.3.

JIRA NVGPU-1921

Change-Id: I7caee762bad03889944c94b44124e673b64e1fbc
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014634
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2019-02-08 15:32:28 +05:30
committed by mobile promotions
parent 75f9486b82
commit cb0d314f23
2 changed files with 9 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c
View File

@@ -122,6 +122,8 @@ static const struct nvlink_reginit nvlink_reginit_per_link_gpu[] = {
static int gv100_nvlink_get_tlc_reginit(enum nvgpu_nvlink_endp endp,
struct nvlink_reginit **reg, u32 *count)
{
int ret = 0;
switch(endp) {
case nvgpu_nvlink_endp_tegra:
*reg = (struct nvlink_reginit *)
@@ -134,10 +136,11 @@ static int gv100_nvlink_get_tlc_reginit(enum nvgpu_nvlink_endp endp,
*count = ARRAY_SIZE(nvlink_reginit_per_link_gpu);
break;
default:
return -EINVAL;
ret = -EINVAL;
break;
}
return 0;
return ret;
}
int gv100_nvlink_reg_init(struct gk20a *g)

5
drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
View File

@@ -1397,7 +1397,8 @@ int gv100_nvlink_link_set_mode(struct gk20a *g, u32 link_id, u32 mode)
/* 1/8 th mode not supported */
case nvgpu_nvlink_link_enable_pm:
case nvgpu_nvlink_link_disable_pm:
return -EPERM;
err = -EPERM;
break;
case nvgpu_nvlink_link_disable_err_detect:
/* Disable Link interrupts */
g->ops.nvlink.intr.dlpl_intr_enable(g, link_id, false);
@@ -1603,6 +1604,8 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
return -EINVAL;
}
nvgpu_err(g, "MODE %u", mode);
err = -EPERM;
break;
}
if (err != 0) {