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gpu: nvgpu: unify cbc_init in cbc and fb units

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Pre-volta, cbc config is part of hw ltc and from volta onwards this is
moved to hw fb. Because of this, cbc_init functions are present in both
cbc unit and fb unit. Pre-volta uses cbc_init from cbc unit and from
volta onwards it uses cbc_init from fb unit.

With this patch, unified two cbc_init functions to cbc unit and created
new fb hal for cbc_configure. cbc unit uses fb hal for cbc_config and
fb unit is independent of cbc unit.

JIRA NVGPU-2897

Change-Id: Ib62f0b08547b031bcb5011c837e43c74931a22fe
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030906
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-03-01 14:18:51 -08:00
committed by mobile promotions
parent a3289cb80c
commit cc74fd9303
15 changed files with 101 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile
View File

@@ -180,6 +180,7 @@ nvgpu-y += \
hal/power_features/cg/tu104_gating_reglist.o \
hal/cbc/cbc_gm20b.o \
hal/cbc/cbc_gp10b.o \
hal/cbc/cbc_gv11b.o \
hal/cbc/cbc_tu104.o \
hal/fuse/fuse_gm20b.o \
hal/fuse/fuse_gp10b.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -346,6 +346,7 @@ srcs += common/sim.c \
hal/power_features/cg/tu104_gating_reglist.c \
hal/cbc/cbc_gm20b.c \
hal/cbc/cbc_gp10b.c \
hal/cbc/cbc_gv11b.c \
hal/cbc/cbc_tu104.c \
hal/fuse/fuse_gm20b.c \
hal/fuse/fuse_gp10b.c \

8
drivers/gpu/nvgpu/common/fb/fb_gv11b.c
View File

@@ -121,11 +121,8 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
}
}
void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
void gv11b_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
{
u32 max_size = gr->max_comptag_mem;
/* one tag line covers 64KB */
u32 max_comptag_lines = max_size << 4;
u32 compbit_base_post_divide;
u64 compbit_base_post_multiply64;
u64 compbit_store_iova;
@@ -172,9 +169,6 @@ void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
gr->compbit_store.base_hw = compbit_base_post_divide;
g->ops.cbc.ctrl(g, gk20a_cbc_op_invalidate,
0, max_comptag_lines - 1U);
}
static const char * const invalid_str = "invalid";

4
drivers/gpu/nvgpu/common/fb/fb_gv11b.h
View File

@@ -1,7 +1,7 @@
/*
* GV11B FB
*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -34,7 +34,7 @@ struct gr_gk20a;
void gv11b_fb_init_hw(struct gk20a *g);
void gv11b_fb_init_fs_state(struct gk20a *g);
void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr);
void gv11b_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr);
void gv11b_fb_reset(struct gk20a *g);
void gv11b_fb_hub_isr(struct gk20a *g);

4
drivers/gpu/nvgpu/common/fb/fb_tu104.c
View File

@@ -424,7 +424,7 @@ int fb_tu104_mmu_invalidate_replay(struct gk20a *g,
return err;
}
void fb_tu104_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
void tu104_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
{
u64 base_divisor;
u64 compbit_store_base;
@@ -466,8 +466,6 @@ void fb_tu104_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
gr->compbit_store.base_hw = compbit_store_base;
g->ops.cbc.ctrl(g, gk20a_cbc_op_invalidate,
0, gr->max_comptag_lines - 1U);
}
static int tu104_fb_wait_mmu_bind(struct gk20a *g)

2
drivers/gpu/nvgpu/common/fb/fb_tu104.h
View File

@@ -55,7 +55,7 @@ int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
int fb_tu104_mmu_invalidate_replay(struct gk20a *g,
u32 invalidate_replay_val);
void fb_tu104_init_cbc(struct gk20a *g, struct gr_gk20a *gr);
void tu104_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr);
int tu104_fb_apply_pdb_cache_war(struct gk20a *g);
size_t tu104_fb_get_vidmem_size(struct gk20a *g);

1
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -365,7 +365,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.fb = {
.init_hw = NULL,
.init_fs_state = NULL,
.init_cbc = NULL,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line = NULL,
.compression_page_size = gp10b_fb_compression_page_size,

4
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2815,10 +2815,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
g->ops.cbc.init(g, gr);
}
if (g->ops.fb.init_cbc != NULL) {
g->ops.fb.init_cbc(g, gr);
}
if (g->ops.gr.disable_rd_coalesce != NULL) {
g->ops.gr.disable_rd_coalesce(g);
}

5
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -33,6 +33,7 @@
#include "hal/power_features/cg/gv11b_gating_reglist.h"
#include "hal/cbc/cbc_gm20b.h"
#include "hal/cbc/cbc_gp10b.h"
#include "hal/cbc/cbc_gv11b.h"
#include "hal/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gp10b.h"
@@ -290,7 +291,7 @@ static const struct gpu_ops gv11b_ops = {
.split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
},
.cbc = {
.init = NULL,
.init = gv11b_cbc_init,
.alloc_comptags = gp10b_cbc_alloc_comptags,
.ctrl = gp10b_cbc_ctrl,
},
@@ -567,7 +568,7 @@ static const struct gpu_ops gv11b_ops = {
.fb = {
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gv11b_fb_init_fs_state,
.init_cbc = gv11b_fb_init_cbc,
.cbc_configure = gv11b_fb_cbc_configure,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,

45
drivers/gpu/nvgpu/hal/cbc/cbc_gv11b.c Normal file
View File

@@ -0,0 +1,45 @@
/*
* GP10B CBC
*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/cbc.h>
#include <nvgpu/log.h>
#include <nvgpu/gk20a.h>
#include "cbc_gv11b.h"
void gv11b_cbc_init(struct gk20a *g, struct gr_gk20a *gr)
{
u32 max_size = gr->max_comptag_mem;
/* one tag line covers 64KB */
u32 max_comptag_lines = max_size << 4;
nvgpu_log_fn(g, " ");
g->ops.fb.cbc_configure(g, gr);
g->ops.cbc.ctrl(g, gk20a_cbc_op_invalidate,
0, max_comptag_lines - 1U);
}

30
drivers/gpu/nvgpu/hal/cbc/cbc_gv11b.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef CBC_GV11B_H
#define CBC_GV11B_H
struct gk20a;
struct gpu_ops;
void gv11b_cbc_init(struct gk20a *g, struct gr_gk20a *gr);
#endif

12
drivers/gpu/nvgpu/hal/cbc/cbc_tu104.c
View File

@@ -30,11 +30,12 @@
#include <trace/events/gk20a.h>
#include <nvgpu/hw/tu104/hw_ltc_tu104.h>
#include "cbc_tu104.h"
#include "common/ltc/ltc_gv11b.h"
#include <nvgpu/hw/tu104/hw_ltc_tu104.h>
u64 tu104_cbc_get_base_divisor(struct gk20a *g)
{
@@ -216,3 +217,12 @@ out:
nvgpu_mutex_release(&g->mm.l2_op_lock);
return err;
}
void tu104_cbc_init(struct gk20a *g, struct gr_gk20a *gr)
{
g->ops.fb.cbc_configure(g, gr);
g->ops.cbc.ctrl(g, gk20a_cbc_op_invalidate,
0, gr->max_comptag_lines - 1U);
}

1
drivers/gpu/nvgpu/hal/cbc/cbc_tu104.h
View File

@@ -33,5 +33,6 @@ u64 tu104_cbc_get_base_divisor(struct gk20a *g);
int tu104_cbc_alloc_comptags(struct gk20a *g, struct gr_gk20a *gr);
int tu104_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
u32 min, u32 max);
void tu104_cbc_init(struct gk20a *g, struct gr_gk20a *gr);
#endif

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -658,7 +658,7 @@ struct gpu_ops {
} gr;
struct {
void (*init_hw)(struct gk20a *g);
void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
void (*cbc_configure)(struct gk20a *g, struct gr_gk20a *gr);
void (*init_fs_state)(struct gk20a *g);
void (*init_uncompressed_kind_map)(struct gk20a *g);
void (*init_kind_attr)(struct gk20a *g);

6
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -356,7 +356,7 @@ static const struct gpu_ops tu104_ops = {
.split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
},
.cbc = {
.init = NULL,
.init = tu104_cbc_init,
.get_base_divisor = tu104_cbc_get_base_divisor,
.alloc_comptags = tu104_cbc_alloc_comptags,
.ctrl = tu104_cbc_ctrl,
@@ -637,7 +637,7 @@ static const struct gpu_ops tu104_ops = {
.fb = {
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gp106_fb_init_fs_state,
.init_cbc = fb_tu104_init_cbc,
.cbc_configure = tu104_fb_cbc_configure,
.set_mmu_page_size = NULL,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
@@ -1318,9 +1318,9 @@ int tu104_init_hal(struct gk20a *g)
/* dGpu VDK support */
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){
/* Disable compression */
gops->cbc.init = NULL;
gops->cbc.ctrl = NULL;
gops->cbc.alloc_comptags = NULL;
gops->fb.init_cbc = NULL;
gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;