gpu: nvgpu: update GSP falcon base addr init

GSPLITE falcon base address was being set without invoking hal api.
This patch defines gpu_ops.gsp.falcon_base_addr hal api to get this
base address.

JIRA NVGPU-1587

Change-Id: Id187b34d022f90c09b8762cdab7769323b607cc0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969432
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/falcon/falcon_gv100.c

@@ -64,7 +64,7 @@ int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
 		flcn->is_interrupt_enabled = true;
 		break;
 	case FALCON_ID_GSPLITE:
-		flcn->flcn_base = pgsp_falcon_irqsset_r();
+		flcn->flcn_base = g->ops.gsp.falcon_base_addr();
 		flcn->is_falcon_supported = true;
 		flcn->is_interrupt_enabled = false;
 		break;

drivers/gpu/nvgpu/gv100/gsp_gv100.c

@@ -111,3 +111,8 @@ int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g,
 exit:
 	return err;
 }
+
+u32 gv100_gsp_falcon_base_addr(void)
+{
+	return pgsp_falcon_irqsset_r();
+}

drivers/gpu/nvgpu/gv100/gsp_gv100.h

@@ -27,5 +27,6 @@ int gv100_gsp_reset(struct gk20a *g);
 int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g,
 	struct hs_acr *acr_desc,
 	struct nvgpu_falcon_bl_info *bl_info);
+u32 gv100_gsp_falcon_base_addr(void);
 
 #endif /*GSP_GV100_H */

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -100,6 +100,7 @@
 
 #include "gv100.h"
 #include "hal_gv100.h"
+#include "gsp_gv100.h"
 #include "gv100/bios_gv100.h"
 #include "gv100/fifo_gv100.h"
 #include "gv100/gr_gv100.h"
@@ -1089,6 +1090,9 @@ static const struct gpu_ops gv100_ops = {
 	.sec2 = {
 		.falcon_base_addr = gp106_sec2_falcon_base_addr,
 	},
+	.gsp = {
+		.falcon_base_addr = gv100_gsp_falcon_base_addr,
+	},
 	.chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
 	.get_litter_value = gv100_get_litter_value,
 };
@@ -1133,6 +1137,7 @@ int gv100_init_hal(struct gk20a *g)
 	gops->top = gv100_ops.top;
 	gops->acr = gv100_ops.acr;
 	gops->sec2 = gv100_ops.sec2;
+	gops->gsp = gv100_ops.gsp;
 
 	/* clocks */
 	gops->clk.init_clk_support = gv100_ops.clk.init_clk_support;

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -77,7 +77,6 @@
 #include "gp10b/gr_gp10b.h"
 #include "gp10b/clk_arb_gp10b.h"
 
-
 #include "gv100/gr_gv100.h"
 
 #include "hal_gv11b.h"

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1484,6 +1484,9 @@ struct gpu_ops {
 			u32 *tail, bool set);
 		u32 (*falcon_base_addr)(void);
 	} sec2;
+	struct {
+		u32 (*falcon_base_addr)(void);
+	} gsp;
 	void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
 };
 

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -85,6 +85,8 @@
 #include "gm20b/mm_gm20b.h"
 
 #include "gv100/clk_gv100.h"
+#include "gv100/gsp_gv100.h"
+
 #include "gp106/sec2_gp106.h"
 #include "gp106/bios_gp106.h"
 
@@ -1114,6 +1116,9 @@ static const struct gpu_ops tu104_ops = {
 		.msgq_tail = tu104_sec2_msgq_tail,
 		.falcon_base_addr = tu104_sec2_falcon_base_addr,
 	},
+	.gsp = {
+		.falcon_base_addr = gv100_gsp_falcon_base_addr,
+	},
 	.chip_init_gpu_characteristics = tu104_init_gpu_characteristics,
 	.get_litter_value = tu104_get_litter_value,
 };
@@ -1157,6 +1162,7 @@ int tu104_init_hal(struct gk20a *g)
 	gops->nvlink = tu104_ops.nvlink;
 	gops->acr = tu104_ops.acr;
 	gops->sec2 = tu104_ops.sec2;
+	gops->gsp = tu104_ops.gsp;
 
 	/* clocks */
 	gops->clk.init_clk_support = tu104_ops.clk.init_clk_support;