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Revert "gpu: nvgpu: Implement sparse PDEs"
This reverts commit c44947b1314bb2afa1f116b4928f4e8a4c34d7b1. It introduces a regression in T124. Bug 1702063 Change-Id: I64e333f66d98bd4dbcfe40a60f1aa825d90376a5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/830786 GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
@@ -2164,10 +2164,8 @@ static int update_gmmu_pde_locked(struct vm_gk20a *vm,
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gk20a_dbg_fn("");
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small_valid = !sparse && entry->size
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&& entry->pgsz == gmmu_page_size_small;
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big_valid = !sparse && entry->size
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&& entry->pgsz == gmmu_page_size_big;
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small_valid = entry->size && entry->pgsz == gmmu_page_size_small;
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big_valid = entry->size && entry->pgsz == gmmu_page_size_big;
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if (small_valid)
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pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0);
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@@ -2187,9 +2185,6 @@ static int update_gmmu_pde_locked(struct vm_gk20a *vm,
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(big_valid ? (gmmu_pde_vol_big_true_f()) :
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gmmu_pde_vol_big_false_f());
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if (sparse)
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pde_v[1] |= gmmu_pde_vol_big_true_f();
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pde = pde_from_index(vm, i);
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gk20a_mem_wr32(pde, 0, pde_v[0]);
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@@ -2264,8 +2259,6 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
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} else if (sparse) {
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pte_w[0] = gmmu_pte_valid_false_f();
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pte_w[1] |= gmmu_pte_vol_true_f();
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gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x%08x,0x%08x]",
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i, pte_w[1], pte_w[0]);
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} else {
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gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i);
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}
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@@ -2324,39 +2317,41 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm,
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while (gpu_va < gpu_end) {
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struct gk20a_mm_entry *next_pte = NULL;
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u64 next = (gpu_va + pde_size) & ~(pde_size-1);
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u64 curr = gpu_va & ~(pde_size-1);
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bool sparse_entry = sparse &&
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((gpu_va == curr && gpu_end >= next) ||
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!next_l->update_entry);
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gk20a_dbg(gpu_dbg_pte, "pde_i %d [%llx-%llx] gpu_va %llx sparse %d (%d)\n",
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pde_i, curr, next, gpu_va, sparse_entry, pte->sparse);
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u64 next = min((gpu_va + pde_size) & ~(pde_size-1), gpu_end);
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/* Allocate next level */
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if (!pte->entries) {
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int num_entries =
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1 <<
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(l->hi_bit[pgsz_idx]
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- l->lo_bit[pgsz_idx] + 1);
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pte->entries =
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vzalloc(sizeof(struct gk20a_mm_entry) *
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num_entries);
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if (!pte->entries)
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return -ENOMEM;
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pte->pgsz = pgsz_idx;
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pte->num_entries = num_entries;
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}
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next_pte = pte->entries + pde_i;
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if (next_l->update_entry) {
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if (!pte->entries) {
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int num_entries =
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1 <<
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(l->hi_bit[pgsz_idx]
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- l->lo_bit[pgsz_idx] + 1);
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pte->entries =
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vzalloc(sizeof(struct gk20a_mm_entry) *
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num_entries);
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if (!pte->entries)
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return -ENOMEM;
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pte->pgsz = pgsz_idx;
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pte->num_entries = num_entries;
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}
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next_pte = pte->entries + pde_i;
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if (next_l->update_entry && !sparse_entry) {
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if (!next_pte->size) {
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err = gk20a_zalloc_gmmu_page_table(vm,
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pgsz_idx, next_l, next_pte);
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if (err)
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return err;
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}
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}
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err = l->update_entry(vm, pte, pde_i, pgsz_idx,
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sgl, offset, iova,
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kind_v, ctag, cacheable, unmapped_pte,
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rw_flag, sparse, priv);
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if (err)
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return err;
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if (next_l->update_entry) {
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/* get cpu access to the ptes */
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err = map_gmmu_pages(next_pte);
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if (err) {
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@@ -2365,29 +2360,13 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm,
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vm_aspace_id(vm));
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return err;
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}
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if (next_pte->sparse) {
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u64 null = 0;
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gk20a_dbg(gpu_dbg_pte, "convert sparse PDE to sparse PTE array [%llx,%llx]",
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curr, next);
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err = update_gmmu_level_locked(vm, next_pte,
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pgsz_idx,
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sgl,
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offset,
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&null,
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curr,
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next,
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kind_v, NULL, cacheable, unmapped_pte,
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rw_flag, true, lvl+1, priv);
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next_pte->sparse = false;
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}
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err = update_gmmu_level_locked(vm, next_pte,
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pgsz_idx,
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sgl,
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offset,
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iova,
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gpu_va,
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min(next, gpu_end),
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next,
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kind_v, ctag, cacheable, unmapped_pte,
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rw_flag, sparse, lvl+1, priv);
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unmap_gmmu_pages(next_pte);
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@@ -2396,15 +2375,6 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm,
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return err;
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}
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err = l->update_entry(vm, pte, pde_i, pgsz_idx,
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sgl, offset, iova,
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kind_v, ctag, cacheable, unmapped_pte,
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rw_flag, sparse_entry, priv);
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if (err)
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return err;
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next_pte->sparse = sparse_entry;
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pde_i++;
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gpu_va = next;
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}
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@@ -2471,8 +2441,8 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
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}
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}
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gk20a_dbg(gpu_dbg_map, "size_idx=%d, gpu_va=[%llx,%llx], iova=%llx, sparse=%d",
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pgsz_idx, gpu_va, gpu_end-1, iova, sparse);
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gk20a_dbg(gpu_dbg_map, "size_idx=%d, gpu_va=[%llx,%llx], iova=%llx",
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pgsz_idx, gpu_va, gpu_end-1, iova);
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err = map_gmmu_pages(&vm->pdb);
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if (err) {
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gk20a_err(dev_from_vm(vm),
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@@ -3026,7 +2996,7 @@ int gk20a_vm_free_space(struct gk20a_as_share *as_share,
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va_node->pgsz_idx,
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true,
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gk20a_mem_flag_none,
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false,
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true,
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NULL);
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kfree(va_node);
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}
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@@ -153,7 +153,6 @@ struct gk20a_mm_entry {
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int pgsz;
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struct gk20a_mm_entry *entries;
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int num_entries;
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bool sparse;
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};
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struct priv_cmd_queue {
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