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gpu: nvgpu: add BVEC tests for common.mc unit

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Add BVEC tests for following common.mc unit APIs:
1. nvgpu_mc_intr_stall_unit_config
2. nvgpu_mc_intr_nonstall_unit_config
3. mc.reset_mask

Changed the WARN to nvgpu_err in mc.reset_mask. Invalid inputs are
handled properly.

Updated the MC unit test logic w.r.t mc_intr_en_r, mc_intr_en_set_r
and mc_intr_en_clear_r semantics.

JIRA NVGPU-6399

Change-Id: I6a3ae42ac37cd6b586f6c71de338595e6cb04a37
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2542591
(cherry picked from commit b9908c979e8964a216141cc6ed475c7de2f2cc0b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623631
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2021-06-10 14:42:35 +05:30
committed by mobile promotions
parent e8ba95c74b
commit cdfbd4313b
4 changed files with 140 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
View File

@@ -151,7 +151,7 @@ static u32 gm20b_mc_unit_reset_mask(struct gk20a *g, u32 unit)
mask = mc_enable_ce2_enabled_f();
break;
default:
WARN(true, "unknown reset unit %d", unit);
nvgpu_err(g, "unknown reset unit %d", unit);
break;
}

2
drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
View File

@@ -75,7 +75,7 @@ static u32 mc_gp10b_intr_pending_f(struct gk20a *g, u32 unit)
intr_pending_f = nvgpu_ce_engine_interrupt_mask(g);
break;
default:
nvgpu_err(g, "Invalid MC interrupt unit specified !!!");
nvgpu_err(g, "Invalid MC interrupt unit %u specified", unit);
break;
}

141
userspace/units/mc/nvgpu-mc.c
View File

@@ -50,12 +50,16 @@
#define ACTIVE_GR_ID 1
#define ACTIVE_CE_ID 2
#define STALL_EN_REG mc_intr_en_set_r(NVGPU_CIC_INTR_STALLING)
#define STALL_DIS_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_EN_REG mc_intr_en_set_r(NVGPU_CIC_INTR_NONSTALLING)
#define NONSTALL_DIS_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING)
#define STALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_NONSTALLING)
#define STALL_EN_REG mc_intr_en_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_EN_REG mc_intr_en_r(NVGPU_CIC_INTR_NONSTALLING)
#define STALL_EN_SET_REG mc_intr_en_set_r(NVGPU_CIC_INTR_STALLING)
#define STALL_EN_CLEAR_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_EN_SET_REG mc_intr_en_set_r(NVGPU_CIC_INTR_NONSTALLING)
#define NONSTALL_EN_CLEAR_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING)
#define STALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_NONSTALLING)
struct mc_unit {
u32 num;
@@ -63,7 +67,6 @@ struct mc_unit {
};
static struct mc_unit mc_units[] = {
{ NVGPU_CIC_INTR_UNIT_BUS, mc_intr_pbus_pending_f() },
{ NVGPU_CIC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ NVGPU_CIC_INTR_UNIT_PRIV_RING, mc_intr_priv_ring_pending_f() },
{ NVGPU_CIC_INTR_UNIT_FIFO, mc_intr_pfifo_pending_f() },
{ NVGPU_CIC_INTR_UNIT_LTC, mc_intr_ltc_pending_f() },
@@ -85,6 +88,29 @@ static struct mc_unit mc_units[] = {
static void writel_access_reg_fn(struct gk20a *g,
struct nvgpu_reg_access *access)
{
u32 value;
if (access->addr == STALL_EN_SET_REG) {
value = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG) | access->value;
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, value);
}
if (access->addr == NONSTALL_EN_SET_REG) {
value = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG) | access->value;
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, value);
}
if (access->addr == STALL_EN_CLEAR_REG) {
value = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG) & ~access->value;
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, value);
}
if (access->addr == NONSTALL_EN_CLEAR_REG) {
value = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG) & ~access->value;
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, value);
}
nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
}
@@ -271,15 +297,19 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args)
int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
{
u32 invalid_units[] = {NUM_MC_UNITS, INVALID_UNIT, U32_MAX};
u32 i;
u32 unit;
u32 val;
/* clear regs */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_DIS_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_DIS_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_EN_SET_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_EN_CLEAR_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_SET_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_CLEAR_REG, 0x0);
for (i = 0; i < NUM_MC_UNITS; i++) {
unit = mc_units[i].num;
@@ -287,15 +317,15 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* enable stall intr */
nvgpu_cic_mon_intr_stall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != mc_units[i].bit) {
if ((val & mc_units[i].bit) == 0) {
unit_return_fail(m, "failed to enable stall intr for unit %u val=0x%08x\n",
unit, val);
}
/* disable stall intr */
nvgpu_cic_mon_intr_stall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != mc_units[i].bit) {
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if ((val & mc_units[i].bit) != 0) {
unit_return_fail(m, "failed to disable stall intr for unit %u val=0x%08x\n",
unit, val);
}
@@ -303,36 +333,56 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* enable nonstall intr */
nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != mc_units[i].bit) {
if ((val & mc_units[i].bit) == 0) {
unit_return_fail(m, "failed to enable nonstall intr for unit %u val=0x%08x\n",
unit, val);
}
/* disable stall intr */
nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != mc_units[i].bit) {
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if ((val & mc_units[i].bit) != 0) {
unit_return_fail(m, "failed to disable nonstall intr for unit %u val=0x%08x\n",
unit, val);
}
}
/* negative testing - invalid unit - stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0); /* clear reg */
nvgpu_cic_mon_intr_stall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
val);
}
for (i = 0; i < ARRAY_SIZE(invalid_units); i++) {
/* negative testing - invalid unit enable set - stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0); /* clear en reg */
nvgpu_cic_mon_intr_stall_unit_config(g, invalid_units[i], true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled stall interrupt for invalid unit, val=0x%08x\n",
val);
}
/* negative testing - invalid unit - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear reg */
nvgpu_cic_mon_intr_nonstall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
val);
/* negative testing - invalid unit enable clear - stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, U32_MAX); /* set en reg */
nvgpu_cic_mon_intr_stall_unit_config(g, invalid_units[i], false);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != U32_MAX) {
unit_return_fail(m, "Incorrectly disabled stall interrupt for invalid unit, val=0x%08x\n",
val);
}
/* negative testing - invalid unit enable set - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear en reg */
nvgpu_cic_mon_intr_nonstall_unit_config(g, invalid_units[i], true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled non-stall interrupt for invalid unit, val=0x%08x\n",
val);
}
/* negative testing - invalid unit enable clear - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, U32_MAX); /* set en reg */
nvgpu_cic_mon_intr_nonstall_unit_config(g, invalid_units[i], false);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != U32_MAX) {
unit_return_fail(m, "Incorrectly enabled non-stall interrupt for invalid unit, val=0x%08x\n",
val);
}
}
return UNIT_SUCCESS;
@@ -347,9 +397,12 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* clear regs */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_DIS_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_DIS_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_EN_SET_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_EN_CLEAR_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_SET_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_CLEAR_REG, 0x0);
/* cleanup anything from previous tests */
g->mc.intr_mask_restore[0] = 0U;
@@ -361,20 +414,20 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* pause stall */
nvgpu_cic_mon_intr_stall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0) {
unit_return_fail(m, "failed to pause stall intr\n");
}
/* pause nonstall */
nvgpu_cic_mon_intr_nonstall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != U32_MAX) {
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0) {
unit_return_fail(m, "failed to pause nonstall intr\n");
}
/* resume stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_EN_SET_REG, 0x0);
nvgpu_cic_mon_intr_stall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != expected_stall_val) {
@@ -382,7 +435,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
}
/* resume nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_SET_REG, 0x0);
nvgpu_cic_mon_intr_nonstall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != expected_nonstall_val) {
@@ -390,17 +443,17 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
}
/* clear regs */
nvgpu_posix_io_writel_reg_space(g, STALL_DIS_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_DIS_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, STALL_EN_CLEAR_REG, 0x0);
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_CLEAR_REG, 0x0);
/* mask all */
nvgpu_cic_mon_intr_mask(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0) {
unit_return_fail(m, "failed to mask stall intr\n");
}
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != U32_MAX) {
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0) {
unit_return_fail(m, "failed to mask nonstall intr\n");
}

57
userspace/units/mc/nvgpu-mc.h
View File

@@ -77,35 +77,52 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);
* Description: Validate function of nvgpu_cic_mon_intr_stall_unit_config and
* nvgpu_cic_mon_intr_nonstall_unit_config.
*
* Test Type: Feature, Error guessing
* Test Type: Feature, Error guessing, Boundary Value
*
* Targets: nvgpu_cic_mon_intr_stall_unit_config, nvgpu_cic_mon_intr_nonstall_unit_config,
* mc_gp10b_intr_stall_unit_config, mc_gp10b_intr_nonstall_unit_config
*
* Input: test_mc_setup_env must have been run.
*
* Equivalence classes:
* Variable: unit
* - Valid : { 0 - 7 }
* - Invalid : { 8 - U32_MAX }
* Variable: enable
* - {false, true}
*
* Steps:
* - Set each of the mock registers for enabling & disabling the stall &
* non-stall interrupts to 0.
* non-stall interrupts and the interrupt enabled registers to 0.
* - Loop through table of units:
* - Call nvgpu_cic_mon_intr_stall_unit_config for the unit to enable the stall
* interrupt.
* - Verify the stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_cic_mon_intr_stall_unit_config for the unit to disable the interrupt.
* - Verify the stall interrupt disable register has the bit set for the unit.
* - Verify the stall interrupt enable register has the bit cleared for the unit.
* - Call nvgpu_cic_mon_intr_nonstall_unit_config for the unit to enable the
* non-stall interrupt.
* - Verify the non-stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_cic_mon_intr_nonstall_unit_config for the unit to disable the interrupt.
* - Verify the non-stall interrupt disable register has the bit set for the unit.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_cic_mon_intr_stall_unit_config() with an
* invalid unit number, and verify no bits are set in the stall interrupt
* enable register.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_cic_mon_intr_nonstall_unit_config() with an
* invalid unit number, and verify no bits are set in the non-stall interrupt
* enable register.
* - Verify the non-stall interrupt enable register has the bit cleared for the unit.
* - Loop through combination of invalid "unit" (8, 100, U32_MAX) and "enable"
* (false, true) values:
* - Clear stall interrupt enable register.
* - Call nvgpu_cic_mon_intr_stall_unit_config() with an invalid unit number to attempt
* enabling the interrupt, and verify no bits are set in the stall interrupt
* enable register.
* - Set all bits in stall interrupt enable register.
* - Call nvgpu_cic_mon_intr_stall_unit_config() with an invalid unit number to attempt
* disabling the interrupt, and verify no bits are cleared in the stall interrupt
* enable register.
* - Clear non-stall interrupt enable register.
* - Call nvgpu_cic_mon_intr_nonstall_unit_config() with an invalid unit number to attempt
* enabling the interrupt, and verify no bits are set in the non-stall interrupt
* enable register.
* - Set all bits in non-stall interrupt enable register.
* - Call nvgpu_cic_mon_intr_nonstall_unit_config() with an invalid unit number to attempt
* disabling the interrupt, and verify no bits are cleared in the non-stall interrupt
* enable register.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.
*/
@@ -313,17 +330,25 @@ int test_enable_disable_reset(struct unit_module *m, struct gk20a *g, void *args
*
* Description: Validate functionality of HAL to get reset mask for a unit.
*
* Test Type: Feature, Error guessing
* Test Type: Feature, Error guessing, Boundary Value
*
* Targets: gops_mc.reset_mask, gm20b_mc_reset_mask
*
* Input: test_mc_setup_env must have been run.
*
* Input:
*
* Equivalence classes:
* Variable: unit
* - Valid : { 0 - 3 }
* - Invalid : { INT_MIN - -1 }, {4 - INT_MAX}
*
* Steps:
* - Call the enable HAL API for a number of units and verify the correct
* mask is returned.
* - For branch coverage pass in an invalid Unit number, and verify the mask
* returned is 0.
* mask is returned. This covers the valid class from above.
* - For branch coverage and invalid class coverage pass in an invalid Unit
* numbers {INT_MIN, -1, 4, 100, INT_MAX}, and verify the mask returned
* is 0.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.
*/