gpu: nvgpu: disable ce2 interrupts when unhandled

ce2 interrupts enabled only on gk20a and gm20b when
interrupts are handled through hal

Change-Id: Ib570db8f5f41e71e768b95e781153ec8a5d20015
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/677447
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -49,6 +49,7 @@ nvgpu-y := \
 	gk20a/mc_gk20a.o \
 	gm20b/hal_gm20b.o \
 	gm20b/ltc_gm20b.o \
+	gm20b/ce2_gm20b.o \
 	gm20b/gr_gm20b.o \
 	gm20b/gr_gm20b.o \
 	gm20b/fb_gm20b.o \

drivers/gpu/nvgpu/gk20a/ce2_gk20a.c

@@ -92,4 +92,8 @@ void gk20a_ce2_nonstall_isr(struct gk20a *g)
 
 	return;
 }
-
+void gk20a_init_ce2(struct gpu_ops *gops)
+{
+	gops->ce2.isr_stall = gk20a_ce2_isr;
+	gops->ce2.isr_nonstall = gk20a_ce2_nonstall_isr;
+}

drivers/gpu/nvgpu/gk20a/ce2_gk20a.h

@@ -24,6 +24,7 @@
 #include "channel_gk20a.h"
 #include "tsg_gk20a.h"
 
+void gk20a_init_ce2(struct gpu_ops *gops);
 void gk20a_ce2_isr(struct gk20a *g);
 void gk20a_ce2_nonstall_isr(struct gk20a *g);
 

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -145,6 +145,9 @@ u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g)
 
 	for (i = 0; i < g->fifo.max_engines; i++) {
 		u32 intr_id = g->fifo.engine_info[i].intr_id;
+		if (i == ENGINE_CE2_GK20A &&
+			(!g->ops.ce2.isr_stall || !g->ops.ce2.isr_nonstall))
+			continue;
 
 		if (intr_id)
 			eng_intr_mask |= BIT(intr_id);

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -87,6 +87,10 @@ struct gpu_ops {
 		u32 (*cbc_fix_config)(struct gk20a *g, int base);
 		void (*flush)(struct gk20a *g);
 	} ltc;
+	struct {
+		void (*isr_stall)(struct gk20a *g);
+		void (*isr_nonstall)(struct gk20a *g);
+	} ce2;
 	struct {
 		int (*init_fs_state)(struct gk20a *g);
 		void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset);

drivers/gpu/nvgpu/gk20a/hal_gk20a.c

@@ -42,7 +42,7 @@ static struct gpu_ops gk20a_ops = {
 			gr_gk20a_pg_gr_load_gating_prod,
 		.slcg_therm_load_gating_prod =
 			gr_gk20a_slcg_therm_load_gating_prod,
-	}
+	},
 };
 
 int gk20a_init_hal(struct gk20a *g)
@@ -57,6 +57,7 @@ int gk20a_init_hal(struct gk20a *g)
 	gk20a_init_gr_ops(gops);
 	gk20a_init_fb(gops);
 	gk20a_init_fifo(gops);
+	gk20a_init_ce2(gops);
 	gk20a_init_gr_ctx(gops);
 	gk20a_init_mm(gops);
 	gk20a_init_pmu_ops(gops);

drivers/gpu/nvgpu/gk20a/mc_gk20a.c

@@ -80,8 +80,9 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 
 	if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
 		gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
-	if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id))
-		gk20a_ce2_isr(g);
+	if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
+		&& g->ops.ce2.isr_stall)
+		g->ops.ce2.isr_stall(g);
 	if (mc_intr_0 & mc_intr_0_pfifo_pending_f())
 		gk20a_fifo_isr(g);
 	if (mc_intr_0 & mc_intr_0_pmu_pending_f())
@@ -118,8 +119,9 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g)
 		gk20a_fifo_nonstall_isr(g);
 	if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
 		gk20a_gr_nonstall_isr(g);
-	if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id))
-		gk20a_ce2_nonstall_isr(g);
+	if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
+		&& g->ops.ce2.isr_nonstall)
+		g->ops.ce2.isr_nonstall(g);
 
 	gk20a_writel(g, mc_intr_en_1_r(),
 		mc_intr_en_1_inta_hardware_f());

drivers/gpu/nvgpu/gm20b/ce2_gm20b.c

@@ -0,0 +1,28 @@
+/*
+ * GK20A Graphics Copy Engine  (gr host)
+ *
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*TODO: remove uncecessary */
+#include "gk20a/gk20a.h"
+#include "ce2_gm20b.h"
+
+void gm20b_init_ce2(struct gpu_ops *gops)
+{
+	gops->ce2.isr_stall = gk20a_ce2_isr;
+	gops->ce2.isr_nonstall = gk20a_ce2_nonstall_isr;
+}

drivers/gpu/nvgpu/gm20b/ce2_gm20b.h

@@ -0,0 +1,29 @@
+/*
+ * drivers/video/tegra/host/gk20a/fifo_gk20a.h
+ *
+ * GK20A graphics copy engine (gr host)
+ *
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __CE2_GM20B_H__
+#define __CE2_GM20B_H__
+
+#include "gk20a/channel_gk20a.h"
+#include "gk20a/tsg_gk20a.h"
+
+void gm20b_init_ce2(struct gpu_ops *gops);
+
+#endif /*__CE2_GM20B_H__*/

drivers/gpu/nvgpu/gm20b/fifo_gm20b.c

@@ -1,7 +1,7 @@
 /*
  * GM20B Fifo
  *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -18,6 +18,7 @@
 #include "gk20a/gk20a.h"
 
 #include "ltc_gm20b.h"
+#include "ce2_gm20b.h"
 #include "gr_gm20b.h"
 #include "ltc_gm20b.h"
 #include "fb_gm20b.h"
@@ -81,7 +82,7 @@ static struct gpu_ops gm20b_ops = {
 			gm20b_blcg_pmu_load_gating_prod,
 		.pg_gr_load_gating_prod =
 			gr_gm20b_pg_gr_load_gating_prod,
-	}
+	},
 };
 
 int gm20b_init_hal(struct gk20a *g)
@@ -124,6 +125,7 @@ int gm20b_init_hal(struct gk20a *g)
 	gm20b_init_ltc(gops);
 	gm20b_init_fb(gops);
 	gm20b_init_fifo(gops);
+	gm20b_init_ce2(gops);
 	gm20b_init_gr_ctx(gops);
 	gm20b_init_mm(gops);
 	gm20b_init_pmu_ops(gops);