gpu: nvgpu: allocate struct nvgpu_gr based on enumerated gr count

Add new API nvgpu_grmgr_get_num_gr_instances() that returns number of
GR instance enumerated by GR manager. This just returns number of sys
pipes enabled since it is same as number of GR instances.

For consistency until common.gr supports multiple GR instances
completely, add a temporary macro NVGPU_GR_NUM_INSTANCES and set it
to 1. If this macro is changed to 0 (for local MIG testing), fall
back to use nvgpu_grmgr_get_num_gr_instances() to get enumerated number
of GR instances.

Use a for loop to initialize other variables of struct nvgpu_gr.

Remove unnecessary NULL check in nvgpu_gr_alloc() since struct gk20a
pointer can never be NULL in this path. Also remove corresponding unit
test code.

Jira NVGPU-5648

Change-Id: Id151d634a23235381229044f2a9af89e390886f2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2400151
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr.c

@@ -49,9 +49,18 @@
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include <nvgpu/engines.h>
 #endif
+#include <nvgpu/grmgr.h>
 
 #include "gr_priv.h"
 
+/*
+ * Use this until common.gr is completely updated to support multiple
+ * GR instances. Once that is supported, nvgpu_grmgr_get_num_gr_instances()
+ * should be used to get number of GR instances.
+ * Set this to 0 for local MIG testing.
+ */
+#define NVGPU_GR_NUM_INSTANCES		1
+
 static int gr_alloc_global_ctx_buffers(struct gk20a *g)
 {
 	struct nvgpu_gr *gr = g->gr;
@@ -838,28 +847,36 @@ int nvgpu_gr_init_support(struct gk20a *g)
 int nvgpu_gr_alloc(struct gk20a *g)
 {
 	struct nvgpu_gr *gr = NULL;
-
-	if (g == NULL) {
-		return -EINVAL;
-	}
+	u32 i;
 
 	/* if gr exists return */
 	if (g->gr != NULL) {
 		return 0;
 	}
 
+	g->num_gr_instances = NVGPU_GR_NUM_INSTANCES;
+	if (g->num_gr_instances == 0U) {
+		g->num_gr_instances = nvgpu_grmgr_get_num_gr_instances(g);
+	}
+	if (g->num_gr_instances == 0U) {
+		nvgpu_err(g, "No GR engine enumerated");
+		return -EINVAL;
+	}
+
 	/* Allocate memory for gr struct */
-	gr = nvgpu_kzalloc(g, sizeof(*gr));
-	if (gr == NULL) {
+	g->gr = nvgpu_kzalloc(g, sizeof(*gr) * g->num_gr_instances);
+	if (g->gr == NULL) {
 		return -ENOMEM;
 	}
 
-	g->gr = gr;
+	for (i = 0U; i < g->num_gr_instances; i++) {
+		gr = &g->gr[i];
 
 		nvgpu_cond_init(&gr->init_wq);
 #ifdef CONFIG_NVGPU_NON_FUSA
-	nvgpu_gr_override_ecc_val(g, g->fecs_feature_override_ecc_val);
+		nvgpu_gr_override_ecc_val(gr, g->fecs_feature_override_ecc_val);
 #endif
+	}
 
 	return 0;
 }

drivers/gpu/nvgpu/common/gr/gr_utils.c

@@ -54,9 +54,9 @@ u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g)
 	return g->gr->fecs_feature_override_ecc_val;
 }
 
-void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val)
+void nvgpu_gr_override_ecc_val(struct nvgpu_gr *gr, u32 ecc_val)
 {
-	g->gr->fecs_feature_override_ecc_val = ecc_val;
+	gr->fecs_feature_override_ecc_val = ecc_val;
 }
 #endif
 

drivers/gpu/nvgpu/common/grmgr/grmgr.c

@@ -240,3 +240,12 @@ int nvgpu_grmgr_config_gr_remap_window(struct gk20a *g,
 #endif
 	return err;
 }
+
+u32 nvgpu_grmgr_get_num_gr_instances(struct gk20a *g)
+{
+	/*
+	 * There is only one gr engine instance per syspipe.
+	 * Hence just return number of syspipes here.
+	 */
+	return g->mig.num_gr_sys_pipes_enabled;
+}

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -751,7 +751,10 @@ struct gk20a {
 	struct clk_gk20a clk;
 	struct nvgpu_fifo fifo;
 	struct nvgpu_nvlink_dev nvlink;
+
 	struct nvgpu_gr *gr;
+	u32 num_gr_instances;
+
 	struct nvgpu_fbp *fbp;
 #ifdef CONFIG_NVGPU_SIM
 	struct sim_nvgpu *sim;

drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h

@@ -32,6 +32,7 @@
  * common.gr.utils unit interface
  */
 struct gk20a;
+struct nvgpu_gr;
 struct nvgpu_gr_falcon;
 struct nvgpu_gr_config;
 struct nvgpu_gr_intr;
@@ -99,7 +100,7 @@ struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g);
 #ifdef CONFIG_NVGPU_NON_FUSA
 /* gr variables */
 u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g);
-void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val);
+void nvgpu_gr_override_ecc_val(struct nvgpu_gr *gr, u32 ecc_val);
 #endif
 #ifdef CONFIG_NVGPU_GRAPHICS
 struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/grmgr.h

@@ -33,5 +33,6 @@ int nvgpu_init_gr_manager(struct gk20a *g);
 
 int nvgpu_grmgr_config_gr_remap_window(struct gk20a *g,
 		u32 gr_syspipe_id, bool enable);
+u32 nvgpu_grmgr_get_num_gr_instances(struct gk20a *g);
 
 #endif /* NVGPU_GRMGR_H */

userspace/units/gr/init/nvgpu-gr-init.c

@@ -273,12 +273,6 @@ static int test_gr_alloc_errors(struct gk20a *g)
 		nvgpu_kmem_get_fault_injection();
 	struct nvgpu_gr *local_gr = g->gr;
 
-	/*Set g to NULL */
-	err = nvgpu_gr_alloc(NULL);
-	if (err == 0) {
-		return UNIT_FAIL;
-	}
-
 	/* Free NULL gr */
 	g->gr = NULL;
 	nvgpu_gr_free(g);