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gpu: nvgpu: Support for runlist_max_supported

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nvgpu_next needs support for max_runlist_supported by litter
value. So the function is changed to support.

JIRA NVGPU-5534

Change-Id: I097f6343295049532c46904316314dc82092a46b
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2382882
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Dinesh
2020-07-21 13:55:53 +05:30
committed by Alex Waterman
parent 58ef68e162
commit d0087f3ad8
12 changed files with 23 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/fifo/runlist.c
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@@ -806,7 +806,7 @@ int nvgpu_runlist_setup_sw(struct gk20a *g)
f->runlist_entry_size = g->ops.runlist.entry_size(g); f->runlist_entry_size = g->ops.runlist.entry_size(g);
f->num_runlist_entries = g->ops.runlist.length_max(g); f->num_runlist_entries = g->ops.runlist.length_max(g);
f->max_runlists = g->ops.runlist.count_max(); f->max_runlists = g->ops.runlist.count_max(g);
f->runlist_info = nvgpu_kzalloc(g, nvgpu_safe_mult_u64( f->runlist_info = nvgpu_kzalloc(g, nvgpu_safe_mult_u64(
sizeof(*f->runlist_info), f->max_runlists)); sizeof(*f->runlist_info), f->max_runlists));
if (f->runlist_info == NULL) { if (f->runlist_info == NULL) {

2
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.c
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@@ -35,7 +35,7 @@
#define FECS_MAILBOX_0_ACK_RESTORE 0x4U #define FECS_MAILBOX_0_ACK_RESTORE 0x4U
u32 gk20a_runlist_count_max(void) u32 gk20a_runlist_count_max(struct gk20a *g)
{ {
return fifo_eng_runlist_base__size_1_v(); return fifo_eng_runlist_base__size_1_v();
} }

2
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a.h
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@@ -35,7 +35,7 @@ int gk20a_fifo_reschedule_preempt_next(struct nvgpu_channel *ch,
bool wait_preempt); bool wait_preempt);
#endif #endif
#ifdef CONFIG_NVGPU_HAL_NON_FUSA #ifdef CONFIG_NVGPU_HAL_NON_FUSA
u32 gk20a_runlist_count_max(void); u32 gk20a_runlist_count_max(struct gk20a *g);
#endif #endif
u32 gk20a_runlist_length_max(struct gk20a *g); u32 gk20a_runlist_length_max(struct gk20a *g);

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv100.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,9 @@
#include "runlist_fifo_gv100.h" #include "runlist_fifo_gv100.h"
#include <nvgpu/hw/gv100/hw_fifo_gv100.h> #include <nvgpu/hw/gv100/hw_fifo_gv100.h>
struct gk20a;
u32 gv100_runlist_count_max(void) u32 gv100_runlist_count_max(struct gk20a *g)
{ {
return fifo_eng_runlist_base__size_1_v(); return fifo_eng_runlist_base__size_1_v();
} }

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv100.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -24,7 +24,8 @@
#define NVGPU_RUNLIST_FIFO_GV100_H #define NVGPU_RUNLIST_FIFO_GV100_H
#include <nvgpu/types.h> #include <nvgpu/types.h>
struct gk20a;
u32 gv100_runlist_count_max(void); u32 gv100_runlist_count_max(struct gk20a *g);
#endif /* NVGPU_RUNLIST_FIFO_GV100_H */ #endif /* NVGPU_RUNLIST_FIFO_GV100_H */

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -26,10 +26,11 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
struct nvgpu_channel; struct nvgpu_channel;
struct gk20a;
#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING #ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
int gv11b_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next); int gv11b_runlist_reschedule(struct nvgpu_channel *ch, bool preempt_next);
#endif #endif
u32 gv11b_runlist_count_max(void); u32 gv11b_runlist_count_max(struct gk20a *g);
#endif /* NVGPU_RUNLIST_FIFO_GV11B_H */ #endif /* NVGPU_RUNLIST_FIFO_GV11B_H */

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gv11b_fusa.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -25,8 +25,9 @@
#include "runlist_fifo_gv11b.h" #include "runlist_fifo_gv11b.h"
#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
struct gk20a;
u32 gv11b_runlist_count_max(void) u32 gv11b_runlist_count_max(struct gk20a *g)
{ {
return fifo_eng_runlist_base__size_1_v(); return fifo_eng_runlist_base__size_1_v();
} }

5
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -27,8 +27,9 @@
#include "runlist_fifo_tu104.h" #include "runlist_fifo_tu104.h"
#include <nvgpu/hw/tu104/hw_fifo_tu104.h> #include <nvgpu/hw/tu104/hw_fifo_tu104.h>
struct gk20a;
u32 tu104_runlist_count_max(void) u32 tu104_runlist_count_max(struct gk20a *g)
{ {
return fifo_runlist_base_lo__size_1_v(); return fifo_runlist_base_lo__size_1_v();
} }

4
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -27,7 +27,7 @@
struct gk20a; struct gk20a;
u32 tu104_runlist_count_max(void); u32 tu104_runlist_count_max(struct gk20a *g);
void tu104_runlist_hw_submit(struct gk20a *g, u32 runlist_id, void tu104_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
u32 count, u32 buffer_index); u32 count, u32 buffer_index);
int tu104_runlist_wait_pending(struct gk20a *g, u32 runlist_id); int tu104_runlist_wait_pending(struct gk20a *g, u32 runlist_id);

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
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@@ -238,6 +238,7 @@ struct railgate_stats {
#define GPU_LIT_SM_SHARED_BASE 46 #define GPU_LIT_SM_SHARED_BASE 46
#define GPU_LIT_GPC_ADDR_WIDTH 47 #define GPU_LIT_GPC_ADDR_WIDTH 47
#define GPU_LIT_TPC_ADDR_WIDTH 48 #define GPU_LIT_TPC_ADDR_WIDTH 48
#define GPU_LIT_MAX_RUNLISTS_SUPPORTED 49
#define nvgpu_get_litter_value(g, v) ((g)->ops.get_litter_value((g), v)) #define nvgpu_get_litter_value(g, v) ((g)->ops.get_litter_value((g), v))

2
drivers/gpu/nvgpu/include/nvgpu/gops_runlist.h
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@@ -73,7 +73,7 @@ struct gops_runlist {
int (*update_for_channel)(struct gk20a *g, u32 runlist_id, int (*update_for_channel)(struct gk20a *g, u32 runlist_id,
struct nvgpu_channel *ch, bool add, struct nvgpu_channel *ch, bool add,
bool wait_for_finish); bool wait_for_finish);
u32 (*count_max)(void); u32 (*count_max)(struct gk20a *g);
u32 (*entry_size)(struct gk20a *g); u32 (*entry_size)(struct gk20a *g);
u32 (*length_max)(struct gk20a *g); u32 (*length_max)(struct gk20a *g);
void (*get_tsg_entry)(struct nvgpu_tsg *tsg, void (*get_tsg_entry)(struct nvgpu_tsg *tsg,

2
userspace/units/fifo/runlist/gv11b/nvgpu-runlist-gv11b.c
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@@ -160,7 +160,7 @@ done:
int test_gv11b_runlist_count_max(struct unit_module *m, int test_gv11b_runlist_count_max(struct unit_module *m,
struct gk20a *g, void *args) struct gk20a *g, void *args)
{ {
if (gv11b_runlist_count_max() != fifo_eng_runlist_base__size_1_v()) { if (gv11b_runlist_count_max(g) != fifo_eng_runlist_base__size_1_v()) {
unit_return_fail(m, "runlist count max value incorrect\n"); unit_return_fail(m, "runlist count max value incorrect\n");
} }