nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 01:50:07 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: select target based on aperture

Browse Source 
While programming ucode's inst block in API
gr_gk20a_load_falcon_bind_instblk(), use gk20a_aperture_mask()
to select target address (i.e. if address is in sysmem or
vidmem) based on aperture

Also add target accessors for gr_fecs_new_ctx and
gr_fecs_arb_ctx_ptr

Jira DNVGPU-22

Change-Id: I88198080f188b349a4448a229dff8416a6a18073
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1216139
(cherry picked from commit 42bc14110df17400dd655bc994dc9e61c73048b1)
Reviewed-on: http://git-master/r/1219703
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-09-06 15:58:16 +05:30
committed by mobile promotions
parent 97512aecb6
commit d07c4b48cf
4 changed files with 54 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2219,12 +2219,16 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g)
inst_ptr = gk20a_mm_inst_block_addr(g, &ucode_info->inst_blk_desc);
gk20a_writel(g, gr_fecs_new_ctx_r(),
gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) |
gr_fecs_new_ctx_target_m() |
gk20a_aperture_mask(g, &ucode_info->inst_blk_desc,
gr_fecs_new_ctx_target_sys_mem_ncoh_f(),
gr_fecs_new_ctx_target_vid_mem_f()) |
gr_fecs_new_ctx_valid_m());
gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(),
gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) |
gr_fecs_arb_ctx_ptr_target_m());
gk20a_aperture_mask(g, &ucode_info->inst_blk_desc,
gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(),
gr_fecs_arb_ctx_ptr_target_vid_mem_f()));
gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7);

16
drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
View File

@@ -1210,6 +1210,14 @@ static inline u32 gr_fecs_new_ctx_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_new_ctx_valid_s(void)
{
return 1;
@@ -1262,6 +1270,14 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_arb_ctx_cmd_r(void)
{
return 0x00409a10;

16
drivers/gpu/nvgpu/gm206/hw_gr_gm206.h
View File

@@ -1206,6 +1206,14 @@ static inline u32 gr_fecs_new_ctx_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_new_ctx_valid_s(void)
{
return 1;
@@ -1258,6 +1266,14 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_arb_ctx_cmd_r(void)
{
return 0x00409a10;

16
drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
View File

@@ -1226,6 +1226,14 @@ static inline u32 gr_fecs_new_ctx_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_new_ctx_valid_s(void)
{
return 1;
@@ -1278,6 +1286,14 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
{
return (r >> 28) & 0x3;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 gr_fecs_arb_ctx_cmd_r(void)
{
return 0x00409a10;