nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: remove g->ops.gr.halt_pipe hal

Browse Source 
Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr
It is called from safe unit, and it calls into API
g->ops.gr.falcon.ctrl_ctxsw() which is also safe

Hence get rid of unsafe API g->ops.gr.halt_pipe().
Caller now directly calls hal.gr.falcon API to halt pipe

Jira NVGPU-3506

Change-Id: I5439cb79431795fc7c22384832cf632d6db03316
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127755
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-05-30 13:35:13 +05:30
committed by mobile promotions
parent e40994c884
commit d16ddb244f
10 changed files with 8 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -550,17 +550,23 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
}
#endif
if (!nvgpu_platform_is_simulation(g)) {
int err = 0;
/*HALT_PIPELINE method, halt GR engine*/
if (g->ops.gr.halt_pipe(g) != 0) {
err = g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_HALT_PIPELINE, 0U, NULL);
if (err != 0) {
nvgpu_err(g, "failed to halt gr pipe");
}
/*
* resetting engine using mc_enable_r() is not
* enough, we do full init sequence
*/
nvgpu_log(g, gpu_dbg_info, "resetting gr engine");
if (g->ops.gr.reset(g) != 0) {
err = g->ops.gr.reset(g);
if (err != 0) {
nvgpu_err(g, "failed to reset gr engine");
}
} else {

6
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -791,12 +791,6 @@ ctxsw_already_enabled:
return err;
}
int nvgpu_gr_halt_pipe(struct gk20a *g)
{
return g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_HALT_PIPELINE, 0U, NULL);
}
void nvgpu_gr_remove_support(struct gk20a *g)
{
if (g->gr->remove_support != NULL) {

1
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -177,7 +177,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
.set_mmu_debug_mode = NULL,
.reset = NULL,
.halt_pipe = NULL,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ctxsw_prog = {

1
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -211,7 +211,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
.set_mmu_debug_mode = NULL,
.reset = NULL,
.halt_pipe = NULL,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ctxsw_prog = {

1
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -189,7 +189,6 @@ static const struct gpu_ops gm20b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ctxsw_prog = {

1
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -222,7 +222,6 @@ static const struct gpu_ops gp10b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ecc = {

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -276,7 +276,6 @@ static const struct gpu_ops gv11b_ops = {
.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ecc = {

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -323,7 +323,6 @@ static const struct gpu_ops tu104_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
.reset = nvgpu_gr_reset,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
.halt_pipe = nvgpu_gr_halt_pipe,
.disable_ctxsw = nvgpu_gr_disable_ctxsw,
.enable_ctxsw = nvgpu_gr_enable_ctxsw,
.ecc = {

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -387,7 +387,6 @@ struct gpu_ops {
int (*reset)(struct gk20a *g);
bool (*esr_bpt_pending_events)(u32 global_esr,
enum nvgpu_event_id_type bpt_event);
int (*halt_pipe)(struct gk20a *g);
int (*disable_ctxsw)(struct gk20a *g);
int (*enable_ctxsw)(struct gk20a *g);
struct {

1
drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
View File

@@ -44,7 +44,6 @@ int nvgpu_gr_alloc(struct gk20a *g);
void nvgpu_gr_free(struct gk20a *g);
int nvgpu_gr_disable_ctxsw(struct gk20a *g);
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_halt_pipe(struct gk20a *g);
void nvgpu_gr_remove_support(struct gk20a *g);
void nvgpu_gr_sw_ready(struct gk20a *g, bool enable);
#endif /* NVGPU_GR_H */