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gpu: nvgpu: Fix MISRA violations in Posix

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Fix violations of MISRA Rule 21.2 in Posix unit.

JIRA NVGPU-6533

Change-Id: I21bb6c4c18f7a904d639bf210bcd3d29f37d69bd
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2486766
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 5239352b4acbe29a7cdb39821e68a717b132d2c9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491861
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
ajesh
2021-02-19 09:14:14 +03:00
committed by mobile promotions
parent 0030dc3eb4
commit d1e836f059
2 changed files with 10 additions and 10 deletions
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6
drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -33,12 +33,12 @@
* Note: this code uses the GCC builtins to implement atomics. * Note: this code uses the GCC builtins to implement atomics.
*/ */
typedef struct __nvgpu_posix_atomic { typedef struct nvgpu_posix_atomic {
/** 32 bit atomic variable. */ /** 32 bit atomic variable. */
atomic_int v; atomic_int v;
} nvgpu_atomic_t; } nvgpu_atomic_t;
typedef struct __nvgpu_posix_atomic64 { typedef struct nvgpu_posix_atomic64 {
/** 64 bit atomic variable. */ /** 64 bit atomic variable. */
atomic_long v; atomic_long v;
} nvgpu_atomic64_t; } nvgpu_atomic64_t;

14
drivers/gpu/nvgpu/include/nvgpu/posix/lock.h
View File

@@ -36,7 +36,7 @@
* *
* This could be revisited later, though. * This could be revisited later, though.
*/ */
struct __nvgpu_posix_lock { struct nvgpu_posix_lock {
/** Pthread mutex structure used internally to implement lock */ /** Pthread mutex structure used internally to implement lock */
pthread_mutex_t mutex; pthread_mutex_t mutex;
}; };
@@ -49,7 +49,7 @@ struct __nvgpu_posix_lock {
* Internal implementation of lock acquire used by public APIs of mutex, * Internal implementation of lock acquire used by public APIs of mutex,
* spinlock and raw spinlock. Uses pthread_mutex_lock to acquire the lock. * spinlock and raw spinlock. Uses pthread_mutex_lock to acquire the lock.
*/ */
static inline void nvgpu_posix_lock_acquire(struct __nvgpu_posix_lock *lock) static inline void nvgpu_posix_lock_acquire(struct nvgpu_posix_lock *lock)
{ {
int err = pthread_mutex_lock(&lock->mutex); int err = pthread_mutex_lock(&lock->mutex);
nvgpu_assert(err == 0); nvgpu_assert(err == 0);
@@ -78,7 +78,7 @@ static inline void nvgpu_posix_lock_acquire(struct __nvgpu_posix_lock *lock)
* the previous owning thread terminated while holding the mutex lock. * the previous owning thread terminated while holding the mutex lock.
*/ */
static inline int nvgpu_posix_lock_try_acquire( static inline int nvgpu_posix_lock_try_acquire(
struct __nvgpu_posix_lock *lock) struct nvgpu_posix_lock *lock)
{ {
return pthread_mutex_trylock(&lock->mutex); return pthread_mutex_trylock(&lock->mutex);
} }
@@ -91,7 +91,7 @@ static inline int nvgpu_posix_lock_try_acquire(
* Internal implementation of lock release used by public APIs of mutex, * Internal implementation of lock release used by public APIs of mutex,
* spinlock and raw spinlock. Uses pthread_mutex_unlock to release the lock. * spinlock and raw spinlock. Uses pthread_mutex_unlock to release the lock.
*/ */
static inline void nvgpu_posix_lock_release(struct __nvgpu_posix_lock *lock) static inline void nvgpu_posix_lock_release(struct nvgpu_posix_lock *lock)
{ {
int err = pthread_mutex_unlock(&lock->mutex); int err = pthread_mutex_unlock(&lock->mutex);
@@ -105,7 +105,7 @@ struct nvgpu_mutex {
* nvgpu lock structure used to implement mutex APIs. This private * nvgpu lock structure used to implement mutex APIs. This private
* structure is a wrapper over pthread_mutex_t. * structure is a wrapper over pthread_mutex_t.
*/ */
struct __nvgpu_posix_lock lock; struct nvgpu_posix_lock lock;
}; };
struct nvgpu_spinlock { struct nvgpu_spinlock {
@@ -114,7 +114,7 @@ struct nvgpu_spinlock {
* structure is a wrapper over pthread_mutex_t. Posix unit * structure is a wrapper over pthread_mutex_t. Posix unit
* implementation of spinlock uses a pthread_mutex_t underneath. * implementation of spinlock uses a pthread_mutex_t underneath.
*/ */
struct __nvgpu_posix_lock lock; struct nvgpu_posix_lock lock;
}; };
struct nvgpu_raw_spinlock { struct nvgpu_raw_spinlock {
@@ -123,7 +123,7 @@ struct nvgpu_raw_spinlock {
* private structure is a wrapper over pthread_mutex_t. Posix unit * private structure is a wrapper over pthread_mutex_t. Posix unit
* implementation of raw spinlock uses a pthread_mutex_t underneath. * implementation of raw spinlock uses a pthread_mutex_t underneath.
*/ */
struct __nvgpu_posix_lock lock; struct nvgpu_posix_lock lock;
}; };
static inline void nvgpu_spinlock_irqsave(struct nvgpu_spinlock *mutex, static inline void nvgpu_spinlock_irqsave(struct nvgpu_spinlock *mutex,